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4  examples/basic/namer.py
@@ -19,10 +19,6 @@ def __init__(self):
19 19
 class Bar:
20 20
 	def __init__(self):
21 21
 		self.sigs = gen_list(2)
22  
-		
23  
-class Toto:
24  
-	def __init__(self):
25  
-		self.sigs = gen_list(2)
26 22
 
27 23
 class Example(Module):
28 24
 	def __init__(self):
31  migen/actorlib/fifo.py
... ...
@@ -0,0 +1,31 @@
  1
+from migen.fhdl.std import *
  2
+from migen.flow.actor import *
  3
+from migen.genlib import fifo
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+
  5
+class _FIFOActor(Module):
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+	def __init__(self, fifo_class, layout, depth):
  7
+		self.sink = Sink(layout)
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+		self.source = Source(layout)
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+		self.busy = Signal()
  10
+
  11
+		###
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+
  13
+		self.submodules.fifo = fifo_class(layout, depth)
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+
  15
+		self.comb += [
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+			self.sink.ack.eq(self.fifo.writable),
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+			self.fifo.we.eq(self.sink.stb),
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+			self.fifo.din.eq(self.sink.payload),
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+
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+			self.source.stb.eq(self.fifo.readable),
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+			self.source.payload.eq(self.fifo.dout),
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+			self.fifo.re.eq(self.source.ack)
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+		]
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+
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+class SyncFIFO(_FIFOActor):
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+	def __init__(self, layout, depth):
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+		_FIFOActor.__init__(self, fifo.SyncFIFO, layout, depth)
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+
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+class AsyncFIFO(_FIFOActor):
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+	def __init__(self, layout, depth):
  31
+		_FIFOActor.__init__(self, fifo.AsyncFIFO, layout, depth)		
15  migen/actorlib/spi.py
@@ -6,6 +6,7 @@
6 6
 from migen.flow.network import *
7 7
 from migen.flow import plumbing
8 8
 from migen.actorlib import misc
  9
+from migen.bank.eventmanager import *
9 10
 
10 11
 # layout is a list of tuples, either:
11 12
 # - (name, nbits, [reset value], [alignment bits])
@@ -109,7 +110,7 @@ def __init__(self, layout, depth=1024):
109 110
 		]
110 111
 
111 112
 class _DMAController(Module):
112  
-	def __init__(self, bus_accessor, bus_aw, bus_dw, mode, base_reset=0, length_reset=0):
  113
+	def __init__(self, bus_accessor, bus_aw, bus_dw, mode, base_reset=0, length_reset=0, generate_irq=False):
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 		self.alignment_bits = bits_for(bus_dw//8) - 1
114 115
 		layout = [
115 116
 			("length", bus_aw + self.alignment_bits, length_reset, self.alignment_bits),
@@ -123,8 +124,18 @@ def __init__(self, bus_accessor, bus_aw, bus_dw, mode, base_reset=0, length_rese
123 124
 		if hasattr(self.generator, "trigger"):
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 			self.trigger = self.generator.trigger
125 126
 
  127
+		self.generate_irq = generate_irq
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+		if generate_irq:
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+			self.submodules.ev = EventManager()
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+			self.ev.done = EventSourceProcess()
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+			self.ev.finalize()
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+			self.comb += self.ev.done.trigger.eq(self.r_busy.status)
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+
126 134
 	def get_csrs(self):
127  
-		return self.generator.get_csrs() + [self.r_busy]
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+		csrs = self.generator.get_csrs() + [self.r_busy]
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+		if self.generate_irq:
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+			csrs += self.ev.get_csrs()
  138
+		return csrs
128 139
 
129 140
 class DMAReadController(_DMAController):
130 141
 	def __init__(self, bus_accessor, *args, **kwargs):

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