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  • 6 commits
  • 3 files changed
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  • 2 contributors
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4 examples/basic/namer.py
@@ -19,10 +19,6 @@ def __init__(self):
class Bar:
def __init__(self):
self.sigs = gen_list(2)
-
-class Toto:
- def __init__(self):
- self.sigs = gen_list(2)
class Example(Module):
def __init__(self):
View
31 migen/actorlib/fifo.py
@@ -0,0 +1,31 @@
+from migen.fhdl.std import *
+from migen.flow.actor import *
+from migen.genlib import fifo
+
+class _FIFOActor(Module):
+ def __init__(self, fifo_class, layout, depth):
+ self.sink = Sink(layout)
+ self.source = Source(layout)
+ self.busy = Signal()
+
+ ###
+
+ self.submodules.fifo = fifo_class(layout, depth)
+
+ self.comb += [
+ self.sink.ack.eq(self.fifo.writable),
+ self.fifo.we.eq(self.sink.stb),
+ self.fifo.din.eq(self.sink.payload),
+
+ self.source.stb.eq(self.fifo.readable),
+ self.source.payload.eq(self.fifo.dout),
+ self.fifo.re.eq(self.source.ack)
+ ]
+
+class SyncFIFO(_FIFOActor):
+ def __init__(self, layout, depth):
+ _FIFOActor.__init__(self, fifo.SyncFIFO, layout, depth)
+
+class AsyncFIFO(_FIFOActor):
+ def __init__(self, layout, depth):
+ _FIFOActor.__init__(self, fifo.AsyncFIFO, layout, depth)
View
15 migen/actorlib/spi.py
@@ -6,6 +6,7 @@
from migen.flow.network import *
from migen.flow import plumbing
from migen.actorlib import misc
+from migen.bank.eventmanager import *
# layout is a list of tuples, either:
# - (name, nbits, [reset value], [alignment bits])
@@ -109,7 +110,7 @@ def __init__(self, layout, depth=1024):
]
class _DMAController(Module):
- def __init__(self, bus_accessor, bus_aw, bus_dw, mode, base_reset=0, length_reset=0):
+ def __init__(self, bus_accessor, bus_aw, bus_dw, mode, base_reset=0, length_reset=0, generate_irq=False):
self.alignment_bits = bits_for(bus_dw//8) - 1
layout = [
("length", bus_aw + self.alignment_bits, length_reset, self.alignment_bits),
@@ -123,8 +124,18 @@ def __init__(self, bus_accessor, bus_aw, bus_dw, mode, base_reset=0, length_rese
if hasattr(self.generator, "trigger"):
self.trigger = self.generator.trigger
+ self.generate_irq = generate_irq
+ if generate_irq:
+ self.submodules.ev = EventManager()
+ self.ev.done = EventSourceProcess()
+ self.ev.finalize()
+ self.comb += self.ev.done.trigger.eq(self.r_busy.status)
+
def get_csrs(self):
- return self.generator.get_csrs() + [self.r_busy]
+ csrs = self.generator.get_csrs() + [self.r_busy]
+ if self.generate_irq:
+ csrs += self.ev.get_csrs()
+ return csrs
class DMAReadController(_DMAController):
def __init__(self, bus_accessor, *args, **kwargs):

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