Skip to content

HTTPS clone URL

Subversion checkout URL

You can clone with
or
.
Download ZIP

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also compare across forks.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also compare across forks.
  • 4 commits
  • 11 files changed
  • 0 commit comments
  • 1 contributor
View
2  examples/basic/psync.py
@@ -12,7 +12,7 @@ def get_fragment(self):
class XilinxMultiReg:
@staticmethod
def lower(dr):
- return XilinxMultiRegImpl(dr.i, dr.idomain, dr.o, dr.odomain, dr.n)
+ return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
ps = PulseSynchronizer("from", "to")
v = verilog.convert(ps, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
View
2  examples/basic/simple_gpio.py
@@ -17,7 +17,7 @@ def __init__(self, ninputs=32, noutputs=32):
###
gpio_in_s = Signal(ninputs)
- self.specials += MultiReg(self.gpio_in, "ext", gpio_in_s, "sys")
+ self.specials += MultiReg(self.gpio_in, gpio_in_s, "sys")
self.comb += [
r_i.field.w.eq(gpio_in_s),
self.gpio_out.eq(r_o.field.r)
View
5 examples/sim/fir.py
@@ -6,10 +6,11 @@
import matplotlib.pyplot as plt
from migen.fhdl.structure import *
+from migen.fhdl.module import Module
from migen.fhdl import verilog
from migen.genlib.misc import optree
from migen.fhdl import autofragment
-from migen.sim.generic import Simulator, PureSimulable
+from migen.sim.generic import Simulator
# A synthesizable FIR filter.
class FIR:
@@ -36,7 +37,7 @@ def get_fragment(self):
# A test bench for our FIR filter.
# Generates a sine wave at the input and records the output.
-class TB(PureSimulable):
+class TB(Module):
def __init__(self, fir, frequency):
self.fir = fir
self.frequency = frequency
View
4 migen/actorlib/sim.py
@@ -1,7 +1,7 @@
from migen.fhdl.structure import *
+from migen.fhdl.module import Module
from migen.flow.actor import *
from migen.flow.transactions import *
-from migen.sim.generic import PureSimulable
# Generators yield None or a tuple of Tokens.
# Tokens for Sink endpoints are pulled and the "value" field filled in.
@@ -9,7 +9,7 @@
#
# NB: the possibility to push several tokens at once is important to interact
# with actors that only accept a group of tokens when all of them are available.
-class TokenExchanger(PureSimulable):
+class TokenExchanger(Module):
def __init__(self, generator, actor):
self.generator = generator
self.actor = actor
View
4 migen/bus/csr.py
@@ -1,8 +1,8 @@
from migen.fhdl.structure import *
from migen.fhdl.specials import Memory
+from migen.fhdl.module import Module
from migen.bus.simple import *
from migen.bus.transactions import *
-from migen.sim.generic import PureSimulable
from migen.bank.description import RegisterField
from migen.genlib.misc import chooser
@@ -19,7 +19,7 @@ def __init__(self):
class Interconnect(SimpleInterconnect):
pass
-class Initiator(PureSimulable):
+class Initiator(Module):
def __init__(self, generator, bus=None):
self.generator = generator
if bus is None:
View
4 migen/bus/memory.py
@@ -1,5 +1,5 @@
+from migen.fhdl.module import Module
from migen.bus.transactions import *
-from migen.sim.generic import PureSimulable
def _byte_mask(orig, dat_w, sel):
r = 0
@@ -15,7 +15,7 @@ def _byte_mask(orig, dat_w, sel):
shift += 8
return r
-class Initiator(PureSimulable):
+class Initiator(Module):
def __init__(self, generator, mem):
self.generator = generator
self.mem = mem
View
9 migen/bus/wishbone.py
@@ -1,10 +1,11 @@
from migen.fhdl.structure import *
from migen.fhdl.specials import Memory
+from migen.fhdl.module import Module
from migen.genlib import roundrobin
from migen.genlib.misc import optree
from migen.bus.simple import *
from migen.bus.transactions import *
-from migen.sim.generic import Proxy, PureSimulable
+from migen.sim.generic import Proxy
_desc = Description(
(M_TO_S, "adr", 30),
@@ -116,7 +117,7 @@ def __init__(self, masters, slaves, register=False):
def get_fragment(self):
return self._arbiter.get_fragment() + self._decoder.get_fragment()
-class Tap(PureSimulable):
+class Tap(Module):
def __init__(self, bus, handler=print):
self.bus = bus
self.handler = handler
@@ -133,7 +134,7 @@ def do_simulation(self, s):
s.rd(self.bus.dat_r))
self.handler(transaction)
-class Initiator(PureSimulable):
+class Initiator(Module):
def __init__(self, generator, bus=None):
self.generator = generator
if bus is None:
@@ -180,7 +181,7 @@ def write(self, address, data, sel):
def can_ack(self, bus):
return True
-class Target(PureSimulable):
+class Target(Module):
def __init__(self, model, bus=None):
if bus is None:
bus = Interface()
View
6 migen/fhdl/specials.py
@@ -4,7 +4,7 @@
from migen.fhdl.verilog import _printexpr as verilog_printexpr
class Special(HUID):
- def rename_clock_domain(self):
+ def rename_clock_domain(self, old, new):
pass
def get_clock_domains(self):
@@ -94,7 +94,7 @@ def get_io(self, name):
if isinstance(item, Instance._IO) and item.name == name:
return item.expr
- def rename_clock_domain(self):
+ def rename_clock_domain(self, old, new):
for cr in filter(lambda x: isinstance(x, Instance._CR), self.items):
if cr.domain == old:
cr.domain = new
@@ -214,7 +214,7 @@ def get_port(self, write_capable=False, async_read=False,
self.ports.append(mp)
return mp
- def rename_clock_domain(self):
+ def rename_clock_domain(self, old, new):
for port in self.ports:
if port.clock_domain == old:
port.clock_domain = new
View
4 migen/flow/hooks.py
@@ -1,8 +1,8 @@
from migen.fhdl.structure import *
+from migen.fhdl.module import Module
from migen.flow.actor import *
-from migen.sim.generic import PureSimulable
-class EndpointSimHook(PureSimulable):
+class EndpointSimHook(Module):
def __init__(self, endpoint):
self.endpoint = endpoint
View
17 migen/genlib/cdc.py
@@ -3,9 +3,8 @@
from migen.fhdl.tools import value_bits_sign, list_signals
class MultiRegImpl:
- def __init__(self, i, idomain, o, odomain, n):
+ def __init__(self, i, o, odomain, n):
self.i = i
- self.idomain = idomain
self.o = o
self.odomain = odomain
@@ -24,14 +23,20 @@ def get_fragment(self):
return Fragment(comb, {self.odomain: o_sync})
class MultiReg(Special):
- def __init__(self, i, idomain, o, odomain, n=2):
+ def __init__(self, i, o, odomain, n=2):
Special.__init__(self)
self.i = i
- self.idomain = idomain
self.o = o
self.odomain = odomain
self.n = n
+ def rename_clock_domain(self, old, new):
+ if self.odomain == old:
+ self.odomain = new
+
+ def get_clock_domains(self):
+ return {self.odomain}
+
def list_ios(self, ins, outs, inouts):
r = set()
if ins:
@@ -42,7 +47,7 @@ def list_ios(self, ins, outs, inouts):
@staticmethod
def lower(dr):
- return MultiRegImpl(dr.i, dr.idomain, dr.o, dr.odomain, dr.n)
+ return MultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
class PulseSynchronizer:
def __init__(self, idomain, odomain):
@@ -66,4 +71,4 @@ def get_fragment(self):
]
return Fragment(comb,
{self.idomain: sync_i, self.odomain: sync_o},
- specials={MultiReg(toggle_i, self.idomain, toggle_o, self.odomain)})
+ specials={MultiReg(toggle_i, toggle_o, self.odomain)})
View
7 migen/sim/generic.py
@@ -203,10 +203,3 @@ def __setattr__(self, name, value):
item = getattr(self._obj, name)
assert(isinstance(item, Signal))
self._sim.wr(item, value)
-
-class PureSimulable:
- def do_simulation(self, s):
- raise NotImplementedError("Need to overload do_simulation")
-
- def get_fragment(self):
- return Fragment(sim=[self.do_simulation])

No commit comments for this range

Something went wrong with that request. Please try again.