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  • 11 files changed
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2  examples/basic/psync.py
@@ -12,7 +12,7 @@ def get_fragment(self):
12 12
 class XilinxMultiReg:
13 13
 	@staticmethod
14 14
 	def lower(dr):
15  
-		return XilinxMultiRegImpl(dr.i, dr.idomain, dr.o, dr.odomain, dr.n)
  15
+		return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
16 16
 
17 17
 ps = PulseSynchronizer("from", "to")
18 18
 v = verilog.convert(ps, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
2  examples/basic/simple_gpio.py
@@ -17,7 +17,7 @@ def __init__(self, ninputs=32, noutputs=32):
17 17
 		###
18 18
 
19 19
 		gpio_in_s = Signal(ninputs)
20  
-		self.specials += MultiReg(self.gpio_in, "ext", gpio_in_s, "sys")
  20
+		self.specials += MultiReg(self.gpio_in, gpio_in_s, "sys")
21 21
 		self.comb += [
22 22
 			r_i.field.w.eq(gpio_in_s),
23 23
 			self.gpio_out.eq(r_o.field.r)
5  examples/sim/fir.py
@@ -6,10 +6,11 @@
6 6
 import matplotlib.pyplot as plt
7 7
 
8 8
 from migen.fhdl.structure import *
  9
+from migen.fhdl.module import Module
9 10
 from migen.fhdl import verilog
10 11
 from migen.genlib.misc import optree
11 12
 from migen.fhdl import autofragment
12  
-from migen.sim.generic import Simulator, PureSimulable
  13
+from migen.sim.generic import Simulator
13 14
 
14 15
 # A synthesizable FIR filter.
15 16
 class FIR:
@@ -36,7 +37,7 @@ def get_fragment(self):
36 37
 
37 38
 # A test bench for our FIR filter.
38 39
 # Generates a sine wave at the input and records the output.
39  
-class TB(PureSimulable):
  40
+class TB(Module):
40 41
 	def __init__(self, fir, frequency):
41 42
 		self.fir = fir
42 43
 		self.frequency = frequency
4  migen/actorlib/sim.py
... ...
@@ -1,7 +1,7 @@
1 1
 from migen.fhdl.structure import *
  2
+from migen.fhdl.module import Module
2 3
 from migen.flow.actor import *
3 4
 from migen.flow.transactions import *
4  
-from migen.sim.generic import PureSimulable
5 5
 
6 6
 # Generators yield None or a tuple of Tokens.
7 7
 # Tokens for Sink endpoints are pulled and the "value" field filled in.
@@ -9,7 +9,7 @@
9 9
 #
10 10
 # NB: the possibility to push several tokens at once is important to interact
11 11
 # with actors that only accept a group of tokens when all of them are available.
12  
-class TokenExchanger(PureSimulable):
  12
+class TokenExchanger(Module):
13 13
 	def __init__(self, generator, actor):
14 14
 		self.generator = generator
15 15
 		self.actor = actor
4  migen/bus/csr.py
... ...
@@ -1,8 +1,8 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.fhdl.specials import Memory
  3
+from migen.fhdl.module import Module
3 4
 from migen.bus.simple import *
4 5
 from migen.bus.transactions import *
5  
-from migen.sim.generic import PureSimulable
6 6
 from migen.bank.description import RegisterField
7 7
 from migen.genlib.misc import chooser
8 8
 
@@ -19,7 +19,7 @@ def __init__(self):
19 19
 class Interconnect(SimpleInterconnect):
20 20
 	pass
21 21
 
22  
-class Initiator(PureSimulable):
  22
+class Initiator(Module):
23 23
 	def __init__(self, generator, bus=None):
24 24
 		self.generator = generator
25 25
 		if bus is None:
4  migen/bus/memory.py
... ...
@@ -1,5 +1,5 @@
  1
+from migen.fhdl.module import Module
1 2
 from migen.bus.transactions import *
2  
-from migen.sim.generic import PureSimulable
3 3
 
4 4
 def _byte_mask(orig, dat_w, sel):
5 5
 	r = 0
@@ -15,7 +15,7 @@ def _byte_mask(orig, dat_w, sel):
15 15
 		shift += 8
16 16
 	return r
17 17
 
18  
-class Initiator(PureSimulable):
  18
+class Initiator(Module):
19 19
 	def __init__(self, generator, mem):
20 20
 		self.generator = generator
21 21
 		self.mem = mem
9  migen/bus/wishbone.py
... ...
@@ -1,10 +1,11 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.fhdl.specials import Memory
  3
+from migen.fhdl.module import Module
3 4
 from migen.genlib import roundrobin
4 5
 from migen.genlib.misc import optree
5 6
 from migen.bus.simple import *
6 7
 from migen.bus.transactions import *
7  
-from migen.sim.generic import Proxy, PureSimulable
  8
+from migen.sim.generic import Proxy
8 9
 
9 10
 _desc = Description(
10 11
 	(M_TO_S,	"adr",		30),
@@ -116,7 +117,7 @@ def __init__(self, masters, slaves, register=False):
116 117
 	def get_fragment(self):
117 118
 		return self._arbiter.get_fragment() + self._decoder.get_fragment()
118 119
 
119  
-class Tap(PureSimulable):
  120
+class Tap(Module):
120 121
 	def __init__(self, bus, handler=print):
121 122
 		self.bus = bus
122 123
 		self.handler = handler
@@ -133,7 +134,7 @@ def do_simulation(self, s):
133 134
 					s.rd(self.bus.dat_r))
134 135
 			self.handler(transaction)
135 136
 
136  
-class Initiator(PureSimulable):
  137
+class Initiator(Module):
137 138
 	def __init__(self, generator, bus=None):
138 139
 		self.generator = generator
139 140
 		if bus is None:
@@ -180,7 +181,7 @@ def write(self, address, data, sel):
180 181
 	def can_ack(self, bus):
181 182
 		return True
182 183
 
183  
-class Target(PureSimulable):
  184
+class Target(Module):
184 185
 	def __init__(self, model, bus=None):
185 186
 		if bus is None:
186 187
 			bus = Interface()
6  migen/fhdl/specials.py
@@ -4,7 +4,7 @@
4 4
 from migen.fhdl.verilog import _printexpr as verilog_printexpr
5 5
 
6 6
 class Special(HUID):
7  
-	def rename_clock_domain(self):
  7
+	def rename_clock_domain(self, old, new):
8 8
 		pass
9 9
 
10 10
 	def get_clock_domains(self):
@@ -94,7 +94,7 @@ def get_io(self, name):
94 94
 			if isinstance(item, Instance._IO) and item.name == name:
95 95
 				return item.expr
96 96
 
97  
-	def rename_clock_domain(self):
  97
+	def rename_clock_domain(self, old, new):
98 98
 		for cr in filter(lambda x: isinstance(x, Instance._CR), self.items):
99 99
 			if cr.domain == old:
100 100
 				cr.domain = new
@@ -214,7 +214,7 @@ def get_port(self, write_capable=False, async_read=False,
214 214
 		self.ports.append(mp)
215 215
 		return mp
216 216
 
217  
-	def rename_clock_domain(self):
  217
+	def rename_clock_domain(self, old, new):
218 218
 		for port in self.ports:
219 219
 			if port.clock_domain == old:
220 220
 				port.clock_domain = new
4  migen/flow/hooks.py
... ...
@@ -1,8 +1,8 @@
1 1
 from migen.fhdl.structure import *
  2
+from migen.fhdl.module import Module
2 3
 from migen.flow.actor import *
3  
-from migen.sim.generic import PureSimulable
4 4
 
5  
-class EndpointSimHook(PureSimulable):
  5
+class EndpointSimHook(Module):
6 6
 	def __init__(self, endpoint):
7 7
 		self.endpoint = endpoint
8 8
 	
17  migen/genlib/cdc.py
@@ -3,9 +3,8 @@
3 3
 from migen.fhdl.tools import value_bits_sign, list_signals
4 4
 
5 5
 class MultiRegImpl:
6  
-	def __init__(self, i, idomain, o, odomain, n):
  6
+	def __init__(self, i, o, odomain, n):
7 7
 		self.i = i
8  
-		self.idomain = idomain
9 8
 		self.o = o
10 9
 		self.odomain = odomain
11 10
 
@@ -24,14 +23,20 @@ def get_fragment(self):
24 23
 		return Fragment(comb, {self.odomain: o_sync})
25 24
 
26 25
 class MultiReg(Special):
27  
-	def __init__(self, i, idomain, o, odomain, n=2):
  26
+	def __init__(self, i, o, odomain, n=2):
28 27
 		Special.__init__(self)
29 28
 		self.i = i
30  
-		self.idomain = idomain
31 29
 		self.o = o
32 30
 		self.odomain = odomain
33 31
 		self.n = n
34 32
 
  33
+	def rename_clock_domain(self, old, new):
  34
+		if self.odomain == old:
  35
+			self.odomain = new
  36
+
  37
+	def get_clock_domains(self):
  38
+		return {self.odomain}
  39
+
35 40
 	def list_ios(self, ins, outs, inouts):
36 41
 		r = set()
37 42
 		if ins:
@@ -42,7 +47,7 @@ def list_ios(self, ins, outs, inouts):
42 47
 
43 48
 	@staticmethod
44 49
 	def lower(dr):
45  
-		return MultiRegImpl(dr.i, dr.idomain, dr.o, dr.odomain, dr.n)
  50
+		return MultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
46 51
 
47 52
 class PulseSynchronizer:
48 53
 	def __init__(self, idomain, odomain):
@@ -66,4 +71,4 @@ def get_fragment(self):
66 71
 		]
67 72
 		return Fragment(comb, 
68 73
 			{self.idomain: sync_i, self.odomain: sync_o},
69  
-			specials={MultiReg(toggle_i, self.idomain, toggle_o, self.odomain)})
  74
+			specials={MultiReg(toggle_i, toggle_o, self.odomain)})
7  migen/sim/generic.py
@@ -203,10 +203,3 @@ def __setattr__(self, name, value):
203 203
 		item = getattr(self._obj, name)
204 204
 		assert(isinstance(item, Signal))
205 205
 		self._sim.wr(item, value)
206  
-
207  
-class PureSimulable:
208  
-	def do_simulation(self, s):
209  
-		raise NotImplementedError("Need to overload do_simulation")
210  
-	
211  
-	def get_fragment(self):
212  
-		return Fragment(sim=[self.do_simulation])

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