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14  doc/fhdl.rst
Source Rendered
@@ -112,7 +112,7 @@ Arrays
112 112
 The ``Array`` object represents lists of other objects that can be indexed by FHDL expressions. It is explicitly possible to:
113 113
 
114 114
 * nest ``Array`` objects to create multidimensional tables.
115  
-* list any Python object in a ``Array`` as long as every expression appearing in a fragment ultimately evaluates to a ``Signal`` for all possible values of the indices. This allows the creation of lists of structured data.
  115
+* list any Python object in a ``Array`` as long as every expression appearing in a module ultimately evaluates to a ``Signal`` for all possible values of the indices. This allows the creation of lists of structured data.
116 116
 * use expressions involving ``Array`` objects in both directions (assignment and reading).
117 117
 
118 118
 For example, this creates a 4x4 matrix of 1-bit signals: ::
@@ -134,15 +134,15 @@ Specials
134 134
 
135 135
 Tri-state I/O
136 136
 =============
137  
-A triplet (O, OE, I) of one-way signals defining a tri-state I/O port is represented by the ``TSTriple`` object. Such objects are only containers for signals that are intended to be later connected to a tri-state I/O buffer, and cannot be used in fragments. Such objects, however, should be kept in the design as long as possible as they allow the individual one-way signals to be manipulated in a non-ambiguous way.
  137
+A triplet (O, OE, I) of one-way signals defining a tri-state I/O port is represented by the ``TSTriple`` object. Such objects are only containers for signals that are intended to be later connected to a tri-state I/O buffer, and cannot be used as module specials. Such objects, however, should be kept in the design as long as possible as they allow the individual one-way signals to be manipulated in a non-ambiguous way.
138 138
 
139  
-The object that can be used in a ``Fragment`` is ``Tristate``, and it behaves exactly like an instance of a tri-state I/O buffer that would be defined as follows: ::
  139
+The object that can be used in as a module special is ``Tristate``, and it behaves exactly like an instance of a tri-state I/O buffer that would be defined as follows: ::
140 140
 
141 141
   Instance("Tristate",
142  
-    Instance.Inout("target", target),
143  
-    Instance.Input("o", o),
144  
-    Instance.Input("oe", oe),
145  
-    Instance.Output("i", i)
  142
+    io_target=target,
  143
+    i_o=o,
  144
+    i_oe=oe,
  145
+    o_i=i
146 146
   )
147 147
 
148 148
 Signals ``target``, ``o`` and ``i`` can have any width, while ``oe`` is 1-bit wide. The ``target`` signal should go to a port and not be used elsewhere in the design. Like modern FPGA architectures, Migen does not support internal tri-states.
2  examples/basic/arrays.py
@@ -21,6 +21,6 @@ def __init__(self):
21 21
 
22 22
 		ina = Array(Signal() for a in range(dx))
23 23
 		outa = Array(Signal() for a in range(dy))
24  
-		self.specials += Instance("test", Instance.Output("O", outa[y]), Instance.Input("I", ina[x]))
  24
+		self.specials += Instance("test", o_O=outa[y], i_I=ina[x])
25 25
 
26 26
 print(verilog.convert(Example()))
3  migen/fhdl/module.py
@@ -2,6 +2,7 @@
2 2
 from itertools import combinations
3 3
 
4 4
 from migen.fhdl.structure import *
  5
+from migen.fhdl.structure import _Fragment
5 6
 from migen.fhdl.specials import Special
6 7
 from migen.fhdl.tools import flat_iteration, rename_clock_domain
7 8
 
@@ -108,7 +109,7 @@ def __getattr__(self, name):
108 109
 				sim = [self.do_simulation]
109 110
 			except AttributeError:
110 111
 				sim = []
111  
-			self._fragment = Fragment(sim=sim)
  112
+			self._fragment = _Fragment(sim=sim)
112 113
 			return self._fragment
113 114
 		elif name == "_submodules":
114 115
 			self._submodules = []
30  migen/fhdl/specials.py
... ...
@@ -1,3 +1,5 @@
  1
+from operator import itemgetter
  2
+
1 3
 from migen.fhdl.structure import *
2 4
 from migen.fhdl.size import bits_for, value_bits_sign
3 5
 from migen.fhdl.tools import *
@@ -68,15 +70,6 @@ def get_tristate(self, target):
68 70
 		return Tristate(target, self.o, self.oe, self.i)
69 71
 
70 72
 class Instance(Special):
71  
-	def __init__(self, of, *items, name=""):
72  
-		Special.__init__(self)
73  
-		self.of = of
74  
-		if name:
75  
-			self.name_override = name
76  
-		else:
77  
-			self.name_override = of
78  
-		self.items = items
79  
-	
80 73
 	class _IO:
81 74
 		def __init__(self, name, expr=None):
82 75
 			self.name = name
@@ -89,11 +82,28 @@ class Output(_IO):
89 82
 		pass
90 83
 	class InOut(_IO):
91 84
 		pass
92  
-
93 85
 	class Parameter:
94 86
 		def __init__(self, name, value):
95 87
 			self.name = name
96 88
 			self.value = value
  89
+
  90
+	def __init__(self, of, *items, name="", **kwargs):
  91
+		Special.__init__(self)
  92
+		self.of = of
  93
+		if name:
  94
+			self.name_override = name
  95
+		else:
  96
+			self.name_override = of
  97
+		self.items = list(items)
  98
+		for k, v in sorted(kwargs.items(), key=itemgetter(1)):
  99
+			item_type, item_name = k.split("_", maxsplit=1)
  100
+			item_class = {
  101
+				"i": Instance.Input,
  102
+				"o": Instance.Output,
  103
+				"io": Instance.InOut,
  104
+				"p": Instance.Parameter
  105
+			}[item_type]
  106
+			self.items.append(item_class(item_name, v))
97 107
 	
98 108
 	def get_io(self, name):
99 109
 		for item in self.items:
10  migen/fhdl/structure.py
@@ -250,7 +250,7 @@ def __getitem__(self, key):
250 250
 
251 251
 (SPECIAL_INPUT, SPECIAL_OUTPUT, SPECIAL_INOUT) = range(3)
252 252
 
253  
-class Fragment:
  253
+class _Fragment:
254 254
 	def __init__(self, comb=None, sync=None, specials=None, clock_domains=None, sim=None):
255 255
 		if comb is None: comb = []
256 256
 		if sync is None: sync = dict()
@@ -258,12 +258,9 @@ def __init__(self, comb=None, sync=None, specials=None, clock_domains=None, sim=
258 258
 		if clock_domains is None: clock_domains = _ClockDomainList()
259 259
 		if sim is None: sim = []
260 260
 		
261  
-		if isinstance(sync, list):
262  
-			sync = {"sys": sync}
263  
-		
264 261
 		self.comb = comb
265 262
 		self.sync = sync
266  
-		self.specials = set(specials)
  263
+		self.specials = specials
267 264
 		self.clock_domains = _ClockDomainList(clock_domains)
268 265
 		self.sim = sim
269 266
 	
@@ -273,8 +270,7 @@ def __add__(self, other):
273 270
 			newsync[k] = v[:]
274 271
 		for k, v in other.sync.items():
275 272
 			newsync[k].extend(v)
276  
-		return Fragment(self.comb + other.comb, newsync,
  273
+		return _Fragment(self.comb + other.comb, newsync,
277 274
 			self.specials | other.specials,
278 275
 			self.clock_domains + other.clock_domains,
279 276
 			self.sim + other.sim)
280  
-
6  migen/fhdl/verilog.py
@@ -2,7 +2,7 @@
2 2
 from operator import itemgetter
3 3
 
4 4
 from migen.fhdl.structure import *
5  
-from migen.fhdl.structure import _Operator, _Slice, _Assign
  5
+from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
6 6
 from migen.fhdl.tools import *
7 7
 from migen.fhdl.size import bits_for, flen
8 8
 from migen.fhdl.namer import Namespace, build_namespace
@@ -232,7 +232,7 @@ def _call_special_classmethod(overrides, obj, method, *args, **kwargs):
232 232
 		return None
233 233
 
234 234
 def _lower_specials_step(overrides, specials):
235  
-	f = Fragment()
  235
+	f = _Fragment()
236 236
 	lowered_specials = set()
237 237
 	for special in sorted(specials, key=lambda x: x.huid):
238 238
 		impl = _call_special_classmethod(overrides, special, "lower")
@@ -286,7 +286,7 @@ def convert(f, ios=None, name="top",
286 286
   special_overrides=dict(),
287 287
   create_clock_domains=True,
288 288
   display_run=False):
289  
-	if not isinstance(f, Fragment):
  289
+	if not isinstance(f, _Fragment):
290 290
 		f = f.get_fragment()
291 291
 	if ios is None:
292 292
 		ios = set()
6  migen/fhdl/visit.py
... ...
@@ -1,7 +1,7 @@
1 1
 from copy import copy
2 2
 
3 3
 from migen.fhdl.structure import *
4  
-from migen.fhdl.structure import _Operator, _Slice, _Assign, _ArrayProxy
  4
+from migen.fhdl.structure import _Operator, _Slice, _Assign, _ArrayProxy, _Fragment
5 5
 
6 6
 class NodeVisitor:
7 7
 	def visit(self, node):
@@ -27,7 +27,7 @@ def visit(self, node):
27 27
 			self.visit_If(node)
28 28
 		elif isinstance(node, Case):
29 29
 			self.visit_Case(node)
30  
-		elif isinstance(node, Fragment):
  30
+		elif isinstance(node, _Fragment):
31 31
 			self.visit_Fragment(node)
32 32
 		elif isinstance(node, (list, tuple)):
33 33
 			self.visit_statements(node)
@@ -127,7 +127,7 @@ def visit(self, node):
127 127
 			return self.visit_If(node)
128 128
 		elif isinstance(node, Case):
129 129
 			return self.visit_Case(node)
130  
-		elif isinstance(node, Fragment):
  130
+		elif isinstance(node, _Fragment):
131 131
 			return self.visit_Fragment(node)
132 132
 		elif isinstance(node, (list, tuple)):
133 133
 			return self.visit_statements(node)
5  migen/sim/generic.py
... ...
@@ -1,4 +1,5 @@
1 1
 from migen.fhdl.std import *
  2
+from migen.fhdl.structure import _Fragment
2 3
 from migen.fhdl import verilog
3 4
 from migen.sim.ipc import *
4 5
 from migen.sim import icarus
@@ -76,13 +77,13 @@ def _call_sim(fragment, simulator):
76 77
 
77 78
 class Simulator:
78 79
 	def __init__(self, fragment, top_level=None, sim_runner=None, sockaddr="simsocket", **vopts):
79  
-		if not isinstance(fragment, Fragment):
  80
+		if not isinstance(fragment, _Fragment):
80 81
 			fragment = fragment.get_fragment()
81 82
 		if top_level is None:
82 83
 			top_level = TopLevel()
83 84
 		if sim_runner is None:
84 85
 			sim_runner = icarus.Runner()		
85  
-		self.fragment = fragment + Fragment(clock_domains=top_level.clock_domains)
  86
+		self.fragment = fragment + _Fragment(clock_domains=top_level.clock_domains)
86 87
 		self.top_level = top_level
87 88
 		self.ipc = Initiator(sockaddr)
88 89
 		self.sim_runner = sim_runner

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