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  • 2 commits
  • 2 files changed
  • 0 commit comments
  • 1 contributor
Commits on Aug 12, 2013
Nina Engelhardt add += operator to fragment e12187a
Nina Engelhardt add ternary operator sel ? a : b 6f9f08f
Showing with 26 additions and 0 deletions.
  1. +16 −0 migen/fhdl/structure.py
  2. +10 −0 migen/fhdl/verilog.py
View
16 migen/fhdl/structure.py
@@ -94,6 +94,9 @@ def __init__(self, op, operands):
self.op = op
self.operands = operands
+def Mux(sel, val1, val0):
+ return _Operator("m", [sel, val1, val0])
+
class _Slice(Value):
def __init__(self, value, start, stop):
Value.__init__(self)
@@ -275,3 +278,16 @@ def __add__(self, other):
self.specials | other.specials,
self.clock_domains + other.clock_domains,
self.sim + other.sim)
+
+ def __iadd__(self, other):
+ newsync = defaultdict(list)
+ for k, v in self.sync.items():
+ newsync[k] = v[:]
+ for k, v in other.sync.items():
+ newsync[k].extend(v)
+ self.comb += other.comb
+ self.sync = newsync
+ self.specials |= other.specials
+ self.clock_domains += other.clock_domains
+ self.sim += other.sim
+ return self
View
10 migen/fhdl/verilog.py
@@ -58,6 +58,16 @@ def _printexpr(ns, node):
r2 = "$signed({1'd0, " + r2 + "})"
r = r1 + " " + node.op + " " + r2
s = s1 or s2
+ elif arity == 3:
+ assert node.op == "m"
+ r2, s2 = _printexpr(ns, node.operands[1])
+ r3, s3 = _printexpr(ns, node.operands[2])
+ if s2 and not s3:
+ r3 = "$signed({1'd0, " + r3 + "})"
+ if s3 and not s2:
+ r2 = "$signed({1'd0, " + r2 + "})"
+ r = r1 + " ? " + r2 + " : " + r3
+ s = s2 or s3
else:
raise TypeError
return "(" + r + ")", s

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