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# ==== Clock input ====
NET "clkin50" LOC = AB11 | IOSTANDARD = LVCMOS33;
NET "clkin50" TNM_NET = "GRPclkin50";
TIMESPEC "TSclkin50" = PERIOD "GRPclkin50" 20 ns HIGH 50%;
# ==== Flash ====
NET "flash_adr(0)" LOC = L22;
NET "flash_adr(1)" LOC = L20;
NET "flash_adr(2)" LOC = K22;
NET "flash_adr(3)" LOC = K21;
NET "flash_adr(4)" LOC = J19;
NET "flash_adr(5)" LOC = H20;
NET "flash_adr(6)" LOC = F22;
NET "flash_adr(7)" LOC = F21;
NET "flash_adr(8)" LOC = K17;
NET "flash_adr(9)" LOC = J17;
NET "flash_adr(10)" LOC = E22;
NET "flash_adr(11)" LOC = E20;
NET "flash_adr(12)" LOC = H18;
NET "flash_adr(13)" LOC = H19;
NET "flash_adr(14)" LOC = F20;
NET "flash_adr(15)" LOC = G19;
NET "flash_adr(16)" LOC = C22;
NET "flash_adr(17)" LOC = C20;
NET "flash_adr(18)" LOC = D22;
NET "flash_adr(19)" LOC = D21;
NET "flash_adr(20)" LOC = F19;
NET "flash_adr(21)" LOC = F18;
NET "flash_adr(22)" LOC = D20;
NET "flash_adr(23)" LOC = D19;
NET "flash_d(0)" LOC = AA20;
NET "flash_d(1)" LOC = U14;
NET "flash_d(2)" LOC = U13;
NET "flash_d(3)" LOC = AA6;
NET "flash_d(4)" LOC = AB6;
NET "flash_d(5)" LOC = W4;
NET "flash_d(6)" LOC = Y4;
NET "flash_d(7)" LOC = Y7;
NET "flash_d(8)" LOC = AA2;
NET "flash_d(9)" LOC = AB2;
NET "flash_d(10)" LOC = V15;
NET "flash_d(11)" LOC = AA18;
NET "flash_d(12)" LOC = AB18;
NET "flash_d(13)" LOC = Y13;
NET "flash_d(14)" LOC = AA12;
NET "flash_d(15)" LOC = AB12;
NET "flash_adr(*)" IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "flash_d(*)" IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 | PULLDOWN;
NET "flash_ce_n" LOC = M21 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "flash_oe_n" LOC = M22 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "flash_we_n" LOC = N20 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "flash_rst_n" LOC = P22 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "flash_sts" LOC = R20 | IOSTANDARD = LVCMOS33 | PULLUP;
# ==== UART ====
NET "uart_rx" LOC = K18 | IOSTANDARD = LVCMOS33 | PULLUP;
NET "uart_tx" LOC = L17 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
# ==== Pushbuttons ====
NET "btn1" LOC = AB4 | IOSTANDARD = LVCMOS33;
NET "btn2" LOC = AA4 | IOSTANDARD = LVCMOS33;
NET "btn3" LOC = AB5 | IOSTANDARD = LVCMOS33;
# ==== LEDs ====
NET "led1" LOC = B16 | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO | DRIVE = 24;
NET "led2" LOC = A16 | IOSTANDARD = LVCMOS33 | SLEW = QUIETIO | DRIVE = 24;
# ==== DDR SDRAM ====
NET "sdram_adr(0)" LOC = B1;
NET "sdram_adr(1)" LOC = B2;
NET "sdram_adr(2)" LOC = H8;
NET "sdram_adr(3)" LOC = J7;
NET "sdram_adr(4)" LOC = E4;
NET "sdram_adr(5)" LOC = D5;
NET "sdram_adr(6)" LOC = K7;
NET "sdram_adr(7)" LOC = F5;
NET "sdram_adr(8)" LOC = G6;
NET "sdram_adr(9)" LOC = C1;
NET "sdram_adr(10)" LOC = C3;
NET "sdram_adr(11)" LOC = D1;
NET "sdram_adr(12)" LOC = D2;
NET "sdram_ba(0)" LOC = A2;
NET "sdram_ba(1)" LOC = E6;
NET "sdram_adr(*)" IOSTANDARD = SSTL2_I;
NET "sdram_ba(*)" IOSTANDARD = SSTL2_I;
NET "sdram_cas_n" LOC = C4 | IOSTANDARD = SSTL2_I;
NET "sdram_cke" LOC = G7 | IOSTANDARD = SSTL2_I;
NET "sdram_cs_n" LOC = F7 | IOSTANDARD = SSTL2_I;
NET "sdram_ras_n" LOC = E5 | IOSTANDARD = SSTL2_I;
NET "sdram_we_n" LOC = D3 | IOSTANDARD = SSTL2_I;
NET "sdram_clk_p" LOC = M3 | IOSTANDARD = SSTL2_I;
NET "sdram_clk_n" LOC = L4 | IOSTANDARD = SSTL2_I;
NET "sdram_dm(0)" LOC = E1;
NET "sdram_dm(1)" LOC = E3;
NET "sdram_dm(2)" LOC = F3;
NET "sdram_dm(3)" LOC = G4;
NET "sdram_dqs(0)" LOC = F1;
NET "sdram_dqs(1)" LOC = F2;
NET "sdram_dqs(2)" LOC = H5;
NET "sdram_dqs(3)" LOC = H6;
NET "sdram_dqs(*)" PULLDOWN;
NET "sdram_dq(0)" LOC = Y2;
NET "sdram_dq(1)" LOC = W3;
NET "sdram_dq(2)" LOC = W1;
NET "sdram_dq(3)" LOC = P8;
NET "sdram_dq(4)" LOC = P7;
NET "sdram_dq(5)" LOC = P6;
NET "sdram_dq(6)" LOC = P5;
NET "sdram_dq(7)" LOC = T4;
NET "sdram_dq(8)" LOC = T3;
NET "sdram_dq(9)" LOC = U4;
NET "sdram_dq(10)" LOC = V3;
NET "sdram_dq(11)" LOC = N6;
NET "sdram_dq(12)" LOC = N7;
NET "sdram_dq(13)" LOC = M7;
NET "sdram_dq(14)" LOC = M8;
NET "sdram_dq(15)" LOC = R4;
NET "sdram_dq(16)" LOC = P4;
NET "sdram_dq(17)" LOC = M6;
NET "sdram_dq(18)" LOC = L6;
NET "sdram_dq(19)" LOC = P3;
NET "sdram_dq(20)" LOC = N4;
NET "sdram_dq(21)" LOC = M5;
NET "sdram_dq(22)" LOC = V2;
NET "sdram_dq(23)" LOC = V1;
NET "sdram_dq(24)" LOC = U3;
NET "sdram_dq(25)" LOC = U1;
NET "sdram_dq(26)" LOC = T2;
NET "sdram_dq(27)" LOC = T1;
NET "sdram_dq(28)" LOC = R3;
NET "sdram_dq(29)" LOC = R1;
NET "sdram_dq(30)" LOC = P2;
NET "sdram_dq(31)" LOC = P1;
NET "sdram_dqs(*)" IOSTANDARD = SSTL2_I;
NET "sdram_dm(*)" IOSTANDARD = SSTL2_I;
NET "sdram_dq(*)" IOSTANDARD = SSTL2_I;
# ==== VGA ====
NET "vga_b(0)" LOC = D11;
NET "vga_b(1)" LOC = C12;
NET "vga_b(2)" LOC = B12;
NET "vga_b(3)" LOC = A12;
NET "vga_b(4)" LOC = C13;
NET "vga_b(5)" LOC = A13;
NET "vga_b(6)" LOC = D14;
NET "vga_b(7)" LOC = C14;
NET "vga_g(0)" LOC = C8;
NET "vga_g(1)" LOC = C9;
NET "vga_g(2)" LOC = A9;
NET "vga_g(3)" LOC = D7;
NET "vga_g(4)" LOC = D8;
NET "vga_g(5)" LOC = D10;
NET "vga_g(6)" LOC = C10;
NET "vga_g(7)" LOC = B10;
NET "vga_r(0)" LOC = C6;
NET "vga_r(1)" LOC = B6;
NET "vga_r(2)" LOC = A6;
NET "vga_r(3)" LOC = C7;
NET "vga_r(4)" LOC = A7;
NET "vga_r(5)" LOC = B8;
NET "vga_r(6)" LOC = A8;
NET "vga_r(7)" LOC = D9;
NET "vga_r(*)" IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "vga_g(*)" IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "vga_b(*)" IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "vga_hsync_n" LOC = A14 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "vga_vsync_n" LOC = C15 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "vga_clk" LOC = A11 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "vga_psave_n" LOC = B14 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
NET "vga_sda" LOC = A15 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
NET "vga_sdc" LOC = D15 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
# ==== Memory card ====
NET "mc_d(0)" LOC = A18;
NET "mc_d(1)" LOC = E16;
NET "mc_d(2)" LOC = C17;
NET "mc_d(3)" LOC = A17;
NET "mc_cmd" LOC = B18 | IOSTANDARD = LVCMOS33 | PULLUP;
NET "mc_clk" LOC = A10 | IOSTANDARD = LVCMOS33;
NET "mc_d(*)" IOSTANDARD = LVCMOS33 | PULLUP;
# ==== AC97 ====
NET "ac97_clk" LOC = C11 | IOSTANDARD = LVCMOS33;
NET "ac97_sin" LOC = C5 | IOSTANDARD = LVCMOS33;
NET "ac97_sout" LOC = A4 | IOSTANDARD = LVCMOS33;
NET "ac97_sync" LOC = A5 | IOSTANDARD = LVCMOS33;
NET "ac97_rst_n" LOC = D6 | IOSTANDARD = LVCMOS33;
NET "ac97_clk" TNM_NET = "GRPac97_clk";
TIMESPEC "TSac97_clk" = PERIOD "GRPac97_clk" 80 HIGH 50%;
# ==== USB ====
NET "usba_spd" LOC = Y5 | IOSTANDARD = LVCMOS33;
NET "usba_oe_n" LOC = Y6 | IOSTANDARD = LVCMOS33;
NET "usba_rcv" LOC = V5 | IOSTANDARD = LVCMOS33;
NET "usba_vp" LOC = U6 | IOSTANDARD = LVCMOS33;
NET "usba_vm" LOC = R7 | IOSTANDARD = LVCMOS33;
NET "usbb_spd" LOC = T7 | IOSTANDARD = LVCMOS33;
NET "usbb_oe_n" LOC = R8 | IOSTANDARD = LVCMOS33;
NET "usbb_rcv" LOC = R9 | IOSTANDARD = LVCMOS33;
NET "usbb_vp" LOC = AB3 | IOSTANDARD = LVCMOS33;
NET "usbb_vm" LOC = Y3 | IOSTANDARD = LVCMOS33;
# ==== Ethernet ====
NET "phy_irq_n" LOC = L19 | IOSTANDARD = LVCMOS33;
NET "phy_rst_n" LOC = R22 | IOSTANDARD = LVCMOS33;
NET "phy_mii_clk" LOC = J20 | IOSTANDARD = LVCMOS33;
NET "phy_mii_data" LOC = J22 | IOSTANDARD = LVCMOS33;
NET "phy_dv" LOC = V21 | IOSTANDARD = LVCMOS33;
NET "phy_rx_clk" LOC = H22 | IOSTANDARD = LVCMOS33;
NET "phy_rx_er" LOC = V22 | IOSTANDARD = LVCMOS33;
NET "phy_rx_data(0)" LOC = U22;
NET "phy_rx_data(1)" LOC = U20;
NET "phy_rx_data(2)" LOC = T22;
NET "phy_rx_data(3)" LOC = T21;
NET "phy_rx_data(*)" IOSTANDARD = LVCMOS33;
NET "phy_tx_en" LOC = N19 | IOSTANDARD = LVCMOS33;
NET "phy_tx_clk" LOC = H21 | IOSTANDARD = LVCMOS33;
NET "phy_tx_er" LOC = M19 | IOSTANDARD = LVCMOS33;
NET "phy_tx_data(0)" LOC = M16;
NET "phy_tx_data(1)" LOC = L15;
NET "phy_tx_data(2)" LOC = P19;
NET "phy_tx_data(3)" LOC = P20;
NET "phy_tx_data(*)" IOSTANDARD = LVCMOS33;
NET "phy_col" LOC = W20 | IOSTANDARD = LVCMOS33;
NET "phy_crs" LOC = W22 | IOSTANDARD = LVCMOS33;
NET "phy_clk" LOC = M20 | IOSTANDARD = LVCMOS33;
# Timing
NET "phy_rx_clk" TNM_NET = "GRPphy_rx_clk";
NET "phy_tx_clk" TNM_NET = "GRPphy_tx_clk";
TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;
TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%;
TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
# ==== Video input ====
NET "videoin_p(0)" LOC = Y18;
NET "videoin_p(1)" LOC = T16;
NET "videoin_p(2)" LOC = T15;
NET "videoin_p(3)" LOC = U17;
NET "videoin_p(4)" LOC = U16;
NET "videoin_p(5)" LOC = V19;
NET "videoin_p(6)" LOC = V18;
NET "videoin_p(7)" LOC = R16;
NET "videoin_p(*)" IOSTANDARD = LVCMOS33;
NET "videoin_hs" LOC = V17 | IOSTANDARD = LVCMOS33;
NET "videoin_vs" LOC = Y17 | IOSTANDARD = LVCMOS33;
NET "videoin_field" LOC = AB14 | IOSTANDARD = LVCMOS33;
NET "videoin_llc" LOC = Y11 | IOSTANDARD = LVCMOS33;
NET "videoin_irq_n" LOC = R15 | IOSTANDARD = LVCMOS33 | PULLUP;
NET "videoin_rst_n" LOC = W17 | IOSTANDARD = LVCMOS33;
# IOSTANDARD = I2C does not work
NET "videoin_sda" LOC = AB17 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | PULLUP;
NET "videoin_sdc" LOC = AA14 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
NET "videoin_llc" TNM_NET = "GRPvideoin";
TIMESPEC "TSvideoin" = PERIOD "GRPvideoin" 35 ns HIGH 50%;
# ==== MIDI ====
NET "midi_tx" LOC = AA21 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
NET "midi_rx" LOC = AB21 | IOSTANDARD = LVCMOS33;
# ==== DMX ====
NET "dmxa_r" LOC = AB20 | IOSTANDARD = LVCMOS33;
NET "dmxa_de" LOC = T18 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
NET "dmxa_d" LOC = T17 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
NET "dmxb_r" LOC = Y19 | IOSTANDARD = LVCMOS33;
NET "dmxb_de" LOC = AB19 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
NET "dmxb_d" LOC = W18 | IOSTANDARD = LVCMOS33 | SLEW = SLOW;
# ==== IR ====
NET "ir_rx" LOC = C16 | IOSTANDARD = LVCMOS33;
# ==== Expansion connector ====
NET "exp(0)" LOC = A20;
NET "exp(1)" LOC = F16;
NET "exp(2)" LOC = A21;
NET "exp(3)" LOC = F17;
NET "exp(4)" LOC = B21;
NET "exp(5)" LOC = H16;
NET "exp(6)" LOC = B22;
NET "exp(7)" LOC = H17;
NET "exp(8)" LOC = G16;
NET "exp(9)" LOC = J16;
NET "exp(10)" LOC = G17;
NET "exp(11)" LOC = K16;
NET "exp(*)" IOSTANDARD = LVCMOS33;
# avoid floating signals
NET "exp(*)" PULLDOWN;
# ==== PCB revision ====
NET "pcb_revision(0)" LOC = AA10;
NET "pcb_revision(1)" LOC = AB10;
NET "pcb_revision(2)" LOC = Y10;
NET "pcb_revision(3)" LOC = Y12;
NET "pcb_revision(*)" IOSTANDARD = LVCMOS33;
NET "pcb_revision(*)" PULLDOWN;
# ==== Timing fixes ====
NET "sys_clk" TNM_NET = "GRPsys";
INST "sdram_adr(*)" TNM = "GRPsdramout";
INST "sdram_ba(*)" TNM = "GRPsdramout";
INST "sdram_cas_n" TNM = "GRPsdramout";
INST "sdram_cke" TNM = "GRPsdramout";
INST "sdram_cs_n" TNM = "GRPsdramout";
INST "sdram_ras_n" TNM = "GRPsdramout";
INST "sdram_we_n" TNM = "GRPsdramout";
TIMESPEC "TSsdramout" = FROM FFS TO "GRPsdramout" 10 ns;
NET "vga/vga_iclk" TNM_NET = "GRPvga";
TIMESPEC "TSvga_async1" = FROM "GRPsys" TO "GRPvga" TIG;
TIMESPEC "TSvga_async2" = FROM "GRPvga" TO "GRPsys" TIG;
OFFSET = OUT 5 ns AFTER "vga_clk";
TIMESPEC "TSac97_async1" = FROM "GRPsys" TO "GRPac97_clk" TIG;
TIMESPEC "TSac97_async2" = FROM "GRPac97_clk" TO "GRPsys" TIG;
TIMESPEC "TSvideoin_async1" = FROM "GRPsys" TO "GRPvideoin" TIG;
TIMESPEC "TSvideoin_async2" = FROM "GRPvideoin" TO "GRPsys" TIG;
NET "usb_clk" TNM_NET = "GRPusb";
TIMESPEC "TSusb_async1" = FROM "GRPsys" TO "GRPusb" TIG;
TIMESPEC "TSusb_async2" = FROM "GRPusb" TO "GRPsys" TIG;
NET "clkin50_b" TNM_NET = "GRPinput";
TIMESPEC "TSusb_async3" = FROM "GRPinput" TO "GRPusb" TIG;
TIMESPEC "TSusb_async4" = FROM "GRPusb" TO "GRPinput" TIG;