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TMU prefetch: fixed compilation errors

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1 parent 70d9ba9 commit 44b92e56a920987e5db594cf05d6ff05ac363c01 @sbourdeauducq sbourdeauducq committed Jul 24, 2011
@@ -68,7 +68,7 @@ reg frag_miss_c_r;
reg frag_miss_d_r;
always @(posedge sys_clk) begin
if(req_ce) begin
- req_valid <= pipe_stb_i;
+ req_valid <= frag_pipe_stb_i;
frag_tadra_r <= frag_tadra;
frag_tadrb_r <= frag_tadrb;
@@ -129,7 +129,7 @@ always @(posedge sys_clk) begin
if(missmask_init)
missmask <= 4'b1111;
if(missmask_we) begin
- case(tag_sel)
+ case(wa_sel)
2'd0: missmask <= missmask & 4'b1110;
2'd1: missmask <= missmask & 4'b1101;
2'd2: missmask <= missmask & 4'b1011;
@@ -55,7 +55,7 @@ assign pipe_ack_o = fetch_en & (~fml_stb | fml_ack);
/* Gather received data */
wire fifo_we;
-tmu2_fifo64to256(
+tmu2_fifo64to256 fifo64to256(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
@@ -79,6 +79,6 @@ always @(posedge sys_clk) begin
bcount <= bcount - 2'd1;
end
-assign busy = pipe_stb_o | fml_stb_o;
+assign busy = pipe_stb_o | fml_stb;
endmodule
@@ -40,8 +40,8 @@ reg [depth+1:0] produce;
reg [depth-1:0] consume;
wire wavail = ~level[depth+2];
-wire w8avail = level < ((1 << (depth + 2)) - 8);
-wire ravail = |(level[depth+2:2]);
+assign w8avail = level < ((1 << (depth + 2)) - 8);
+assign ravail = |(level[depth+2:2]);
wire read = re & ravail;
wire write = we & wavail;
@@ -45,12 +45,10 @@ reg [1:0] ralc;
reg [1:0] rald;
always @(posedge sys_clk) begin
- if(re) begin
- rala <= raa[2:1];
- ralb <= rab[2:1];
- ralc <= rac[2:1];
- rald <= rad[2:1];
- end
+ rala <= raa[2:1];
+ ralb <= rab[2:1];
+ ralc <= rac[2:1];
+ rald <= rad[2:1];
end
always @(*) begin
@@ -86,7 +86,7 @@ always @(posedge sys_clk) begin
if(missmask_init)
missmask <= 4'b1111;
if(missmask_we) begin
- case(tag_sel)
+ case(adr_sel)
2'd0: missmask <= missmask & 4'b1110;
2'd1: missmask <= missmask & 4'b1101;
2'd2: missmask <= missmask & 4'b1011;
@@ -117,7 +117,7 @@ always @(*) begin
pipe_stb_o = 1'b0;
load_en = 1'b0;
- tag_sel = 2'd0;
+ adr_sel = 2'd0;
missmask_init = 1'b0;
missmask_we = 1'b0;
@@ -133,13 +133,13 @@ always @(*) begin
pipe_stb_o = 1'b1;
missmask_we = 1'b1;
if(r_miss_a & missmask[0])
- tag_sel = 2'd0;
+ adr_sel = 2'd0;
else if(r_miss_b & missmask[1])
- tag_sel = 2'd1;
+ adr_sel = 2'd1;
else if(r_miss_c & missmask[2])
- tag_sel = 2'd2;
+ adr_sel = 2'd2;
else if(r_miss_d & missmask[3])
- tag_sel = 2'd3;
+ adr_sel = 2'd3;
else begin
pipe_stb_o = 1'b0;
next_state = LOAD;
@@ -177,9 +177,9 @@ assign miss_b = lead_b_r & (ct_b_r != tag_rd_b);
assign miss_c = lead_c_r & (ct_c_r != tag_rd_c);
assign miss_d = lead_d_r & (ct_d_r != tag_rd_d);
-wire more_than_one_miss = (missd_a & missd_b) | (missd_a & missd_c) | (missd_a & missd_d)
- | (missd_b & missd_c) | (missd_b & missd_d)
- | (missd_c & missd_d);
+wire more_than_one_miss = (miss_a & miss_b) | (miss_a & miss_c) | (miss_a & miss_d)
+ | (miss_b & miss_c) | (miss_b & miss_d)
+ | (miss_c & miss_d);
/* Tag rewrite */
reg [1:0] tag_sel;
@@ -254,13 +254,13 @@ always @(*) begin
pipe_stb_o = 1'b1;
busy = 1'b1;
tag_we = 1'b1;
- if(missd_a)
+ if(miss_a)
tag_sel = 2'd0;
- else if(missd_b)
+ else if(miss_b)
tag_sel = 2'd1;
- else if(missd_c)
+ else if(miss_c)
tag_sel = 2'd2;
- else if(missd_d)
+ else if(miss_d)
tag_sel = 2'd3;
else
tag_we = 1'b0;
@@ -280,13 +280,13 @@ always @(*) begin
busy = 1'b1;
tag_we = 1'b1;
missmask_we = 1'b1;
- if(missd_a & missmask[0])
+ if(miss_a & missmask[0])
tag_sel = 2'd0;
- else if(missd_b & missmask[1])
+ else if(miss_b & missmask[1])
tag_sel = 2'd1;
- else if(missd_c & missmask[2])
+ else if(miss_c & missmask[2])
tag_sel = 2'd2;
- else if(missd_d & missmask[3])
+ else if(miss_d & missmask[3])
tag_sel = 2'd3;
else begin
tag_we = 1'b0;
@@ -29,15 +29,15 @@ module tmu2_texmem #(
input sys_rst,
output [fml_depth-1:0] fml_adr,
- output reg fml_stb,
+ output fml_stb,
input fml_ack,
input [63:0] fml_di,
input flush,
output busy,
input pipe_stb_i,
- output reg pipe_ack_o,
+ output pipe_ack_o,
input [fml_depth-1-1:0] dadr, /* in 16-bit words */
input [fml_depth-1-1:0] tadra,
input [fml_depth-1-1:0] tadrb,
@@ -298,7 +298,7 @@ tmu2_buffer #(
wire serialize_busy;
wire serialize_pipe_stb;
wire serialize_pipe_ack;
-wire [fml_depth-5-1:0] serialize_adr
+wire [fml_depth-5-1:0] serialize_adr;
tmu2_serialize #(
.fml_depth(fml_depth)
) serialize (
@@ -402,6 +402,6 @@ tmu2_datamem #(
assign busy = tagmem_busy|split_busy
|fragf_busy
|fetchf_busy|serialize_busy|fetchtexel_busy
- |datemem_busy;
+ |datamem_busy;
endmodule
@@ -2,35 +2,7 @@
#
ARBSRC?=$(wildcard ../../fmlarb/rtl/*)
-SOURCES= \
-../rtl/tmu2_adrgen.v \
-../rtl/tmu2_clamp.v \
-../rtl/tmu2_dpram.v \
-../rtl/tmu2_dpram_sw.v \
-../rtl/tmu2_hdiv.v \
-../rtl/tmu2_burst.v \
-../rtl/tmu2_pixout.v \
-../rtl/tmu2.v\
-../rtl/tmu2_ctlif.v \
-../rtl/tmu2_fetchvertex.v \
-../rtl/tmu2_hinterp.v \
-../rtl/tmu2_qpram32.v \
-../rtl/tmu2_vdivops.v \
-../rtl/tmu2_blend.v \
-../rtl/tmu2_mult2.v \
-../rtl/tmu2_decay.v \
-../rtl/tmu2_geninterp18.v \
-../rtl/tmu2_mask.v \
-../rtl/tmu2_qpram.v \
-../rtl/tmu2_vdiv.v \
-../rtl/tmu2_divider17.v \
-../rtl/tmu2_hdivops.v \
-../rtl/tmu2_texcache.v \
-../rtl/tmu2_vinterp.v \
-../rtl/tmu2_fdest.v \
-../rtl/tmu2_alpha.v \
-../rtl/tmu2_buffer.v \
-$(ARBSRC)
+SOURCES=$(wildcard ../rtl/*) $(ARBSRC)
all: sim

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