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softusb: new DPLL

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commit 81eddbdf593f1354fbe93a1bed535b966163f056 1 parent 4c22685
Sébastien Bourdeauducq authored November 23, 2011

Showing 1 changed file with 35 additions and 17 deletions. Show diff stats Hide diff stats

  1. 52  cores/softusb/rtl/softusb_rx.v
52  cores/softusb/rtl/softusb_rx.v
... ...
@@ -1,6 +1,6 @@
1 1
 /*
2 2
  * Milkymist SoC
3  
- * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
  3
+ * Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
4 4
  *
5 5
  * This program is free software: you can redistribute it and/or modify
6 6
  * it under the terms of the GNU General Public License as published by
@@ -105,26 +105,44 @@ always @(*) begin
105 105
 end
106 106
 
107 107
 /* DPLL */
108  
-reg rx_r;
109  
-always @(posedge usb_clk)
110  
-	rx_r <= rx;
111  
-wire transition = (rx != rx_r);
  108
+reg [2:0] div8_counter;
  109
+reg div8_ce;
  110
+initial div8_counter <= 3'd0;
  111
+always @(posedge usb_clk) begin
  112
+	div8_counter <= div8_counter + 3'd1;
  113
+	div8_ce <= div8_counter == 3'd0;
  114
+end
  115
+
  116
+wire speed_ce = ~low_speed | div8_ce;
  117
+
  118
+reg [3:0] dpll_state;
  119
+reg [3:0] dpll_next_state;
112 120
 
113  
-reg [4:0] dpll_counter;
114  
-reg dpll_ce;
115 121
 always @(posedge usb_clk) begin
116  
-	if(rxreset) begin
117  
-		dpll_counter <= 5'd0;
118  
-		dpll_ce <= 1'b0;
119  
-	end else begin
120  
-		if(transition)
121  
-			dpll_counter <= 5'd0;
122  
-		else
123  
-			dpll_counter <= dpll_counter + 5'd1;
124  
-		dpll_ce <= low_speed ? (dpll_counter == 5'd13) : (transition|(dpll_counter[1:0] == 2'd3));
125  
-	end
  122
+	if(rxreset)
  123
+		dpll_state <= 4'h5;
  124
+	else if(speed_ce)
  125
+		dpll_state <= dpll_next_state;
126 126
 end
127 127
 
  128
+always @(*) begin
  129
+	dpll_next_state = dpll_state;
  130
+	case(dpll_state)
  131
+		4'h5: dpll_next_state = 4'h7;
  132
+		4'h7: if( rx_corrected) dpll_next_state = 4'h6; else dpll_next_state = 4'hb;
  133
+		4'h6: if( rx_corrected) dpll_next_state = 4'h4; else dpll_next_state = 4'h1;
  134
+		4'h4: if( rx_corrected) dpll_next_state = 4'h5; else dpll_next_state = 4'h1;
  135
+		4'h1: dpll_next_state = 4'h3;
  136
+		4'h3: if(~rx_corrected) dpll_next_state = 4'h2; else dpll_next_state = 4'hf;
  137
+		4'h2: if(~rx_corrected) dpll_next_state = 4'h0; else dpll_next_state = 4'h5;
  138
+		4'h0: if(~rx_corrected) dpll_next_state = 4'h1; else dpll_next_state = 4'h5;
  139
+		4'hb: dpll_next_state = 4'h2;
  140
+		4'hf: dpll_next_state = 4'h6;
  141
+	endcase
  142
+end
  143
+
  144
+wire dpll_ce = speed_ce & (dpll_next_state[1] & ~dpll_state[1]);
  145
+
128 146
 /* Serial->Parallel converter */
129 147
 
130 148
 reg [2:0] bitcount;

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