Skip to content

HTTPS clone URL

Subversion checkout URL

You can clone with
or
.
Download ZIP
Browse files

FML: early ack

  • Loading branch information...
commit 8cfa0da32a1550be26bad60e3a67bc9d5d4bd81b 1 parent 7dda0b9
@sbourdeauducq sbourdeauducq authored
View
6 boards/milkymist-one/rtl/ddram.v
@@ -1,6 +1,6 @@
/*
* Milkymist SoC
- * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
+ * Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -34,7 +34,7 @@ module ddram #(
input [`SDRAM_DEPTH-1:0] fml_adr,
input fml_stb,
input fml_we,
- output fml_ack,
+ output fml_eack,
input [7:0] fml_sel,
input [63:0] fml_di,
output [63:0] fml_do,
@@ -101,7 +101,7 @@ hpdmc #(
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
- .fml_ack(fml_ack),
+ .fml_eack(fml_eack),
.fml_sel(fml_sel),
.fml_di(fml_di),
.fml_do(fml_do),
View
8 boards/milkymist-one/rtl/system.v
@@ -562,7 +562,7 @@ wire [63:0] fml_brg_dr,
wire [`SDRAM_DEPTH-1:0] fml_adr;
wire fml_stb;
wire fml_we;
-wire fml_ack;
+wire fml_eack;
wire [7:0] fml_sel;
wire [63:0] fml_dw;
wire [63:0] fml_dr;
@@ -634,7 +634,7 @@ fmlarb #(
.s_adr(fml_adr),
.s_stb(fml_stb),
.s_we(fml_we),
- .s_ack(fml_ack),
+ .s_eack(fml_eack),
.s_sel(fml_sel),
.s_di(fml_dr),
.s_do(fml_dw)
@@ -942,7 +942,7 @@ ddram #(
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
- .fml_ack(fml_ack),
+ .fml_eack(fml_eack),
.fml_sel(fml_sel),
.fml_di(fml_dw),
.fml_do(fml_dr),
@@ -1312,7 +1312,7 @@ fmlmeter #(
.csr_do(csr_dr_fmlmeter),
.fml_stb(fml_stb),
- .fml_ack(fml_ack),
+ .fml_ack(fml_eack),
.fml_we(fml_we),
.fml_adr(fml_adr)
);
View
149 cores/fmlarb/rtl/fmlarb.v
@@ -1,6 +1,6 @@
/*
* Milkymist SoC
- * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
+ * Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -73,7 +73,7 @@ module fmlarb #(
output reg [fml_depth-1:0] s_adr,
output reg s_stb,
output reg s_we,
- input s_ack,
+ input s_eack,
output reg [7:0] s_sel,
input [63:0] s_di,
output reg [63:0] s_do
@@ -86,6 +86,13 @@ assign m3_do = s_di;
assign m4_do = s_di;
assign m5_do = s_di;
+wire m0_stbm;
+wire m1_stbm;
+wire m2_stbm;
+wire m3_stbm;
+wire m4_stbm;
+wire m5_stbm;
+
reg [2:0] master;
reg [2:0] next_master;
@@ -102,114 +109,116 @@ always @(*) begin
next_master = master;
case(master)
- 3'd0: if(~m0_stb | s_ack) begin
- if(m1_stb) next_master = 3'd1;
- else if(m2_stb) next_master = 3'd2;
- else if(m3_stb) next_master = 3'd3;
- else if(m4_stb) next_master = 3'd4;
- else if(m5_stb) next_master = 3'd5;
- end
- 3'd1: if(~m1_stb | s_ack) begin
- if(m0_stb) next_master = 3'd0;
- else if(m3_stb) next_master = 3'd3;
- else if(m4_stb) next_master = 3'd4;
- else if(m5_stb) next_master = 3'd5;
- else if(m2_stb) next_master = 3'd2;
- end
- 3'd2: if(~m2_stb | s_ack) begin
- if(m0_stb) next_master = 3'd0;
- else if(m3_stb) next_master = 3'd3;
- else if(m4_stb) next_master = 3'd4;
- else if(m5_stb) next_master = 3'd5;
- else if(m1_stb) next_master = 3'd1;
- end
- 3'd3: if(~m3_stb | s_ack) begin
- if(m0_stb) next_master = 3'd0;
- else if(m4_stb) next_master = 3'd4;
- else if(m5_stb) next_master = 3'd5;
- else if(m1_stb) next_master = 3'd1;
- else if(m2_stb) next_master = 3'd2;
- end
- 3'd4: if(~m4_stb | s_ack) begin
- if(m0_stb) next_master = 3'd0;
- else if(m5_stb) next_master = 3'd5;
- else if(m1_stb) next_master = 3'd1;
- else if(m2_stb) next_master = 3'd2;
- else if(m3_stb) next_master = 3'd3;
- end
- default: if(~m5_stb | s_ack) begin // 3'd5
- if(m0_stb) next_master = 3'd0;
- else if(m1_stb) next_master = 3'd1;
- else if(m2_stb) next_master = 3'd2;
- else if(m3_stb) next_master = 3'd3;
- else if(m4_stb) next_master = 3'd4;
+ 3'd0: if(~m0_stbm | s_eack) begin
+ if(m1_stbm) next_master = 3'd1;
+ else if(m2_stbm) next_master = 3'd2;
+ else if(m3_stbm) next_master = 3'd3;
+ else if(m4_stbm) next_master = 3'd4;
+ else if(m5_stbm) next_master = 3'd5;
+ end
+ 3'd1: if(~m1_stbm | s_eack) begin
+ if(m0_stbm) next_master = 3'd0;
+ else if(m3_stbm) next_master = 3'd3;
+ else if(m4_stbm) next_master = 3'd4;
+ else if(m5_stbm) next_master = 3'd5;
+ else if(m2_stbm) next_master = 3'd2;
+ end
+ 3'd2: if(~m2_stbm | s_eack) begin
+ if(m0_stbm) next_master = 3'd0;
+ else if(m3_stbm) next_master = 3'd3;
+ else if(m4_stbm) next_master = 3'd4;
+ else if(m5_stbm) next_master = 3'd5;
+ else if(m1_stbm) next_master = 3'd1;
+ end
+ 3'd3: if(~m3_stbm | s_eack) begin
+ if(m0_stbm) next_master = 3'd0;
+ else if(m4_stbm) next_master = 3'd4;
+ else if(m5_stbm) next_master = 3'd5;
+ else if(m1_stbm) next_master = 3'd1;
+ else if(m2_stbm) next_master = 3'd2;
+ end
+ 3'd4: if(~m4_stbm | s_eack) begin
+ if(m0_stbm) next_master = 3'd0;
+ else if(m5_stbm) next_master = 3'd5;
+ else if(m1_stbm) next_master = 3'd1;
+ else if(m2_stbm) next_master = 3'd2;
+ else if(m3_stbm) next_master = 3'd3;
+ end
+ default: if(~m5_stbm | s_eack) begin // 3'd5
+ if(m0_stbm) next_master = 3'd0;
+ else if(m1_stbm) next_master = 3'd1;
+ else if(m2_stbm) next_master = 3'd2;
+ else if(m3_stbm) next_master = 3'd3;
+ else if(m4_stbm) next_master = 3'd4;
end
endcase
end
-/* Generate ack signals */
-assign m0_ack = (master == 3'd0) & s_ack;
-assign m1_ack = (master == 3'd1) & s_ack;
-assign m2_ack = (master == 3'd2) & s_ack;
-assign m3_ack = (master == 3'd3) & s_ack;
-assign m4_ack = (master == 3'd4) & s_ack;
-assign m5_ack = (master == 3'd5) & s_ack;
-
/* Mux control signals */
always @(*) begin
case(master)
3'd0: begin
s_adr = m0_adr;
- s_stb = m0_stb;
+ s_stb = m0_stbm;
s_we = m0_we;
end
3'd1: begin
s_adr = m1_adr;
- s_stb = m1_stb;
+ s_stb = m1_stbm;
s_we = m1_we;
end
3'd2: begin
s_adr = m2_adr;
- s_stb = m2_stb;
+ s_stb = m2_stbm;
s_we = m2_we;
end
3'd3: begin
s_adr = m3_adr;
- s_stb = m3_stb;
+ s_stb = m3_stbm;
s_we = m3_we;
end
3'd4: begin
s_adr = m4_adr;
- s_stb = m4_stb;
+ s_stb = m4_stbm;
s_we = m4_we;
end
default: begin // 3'd5
s_adr = m5_adr;
- s_stb = m5_stb;
+ s_stb = m5_stbm;
s_we = m5_we;
end
endcase
end
-/* Mux data write signals */
-wire write_burst_start = s_we & s_ack;
+/* Generate delayed ack signals and masked strobes */
+fmlarb_dack dack0(.sys_clk(sys_clk), .sys_rst(sys_rst),
+ .stb(m0_stb), .eack((master == 3'd0) & s_eack), .we(m0_we),
+ .stbm(m0_stbm), .ack(m0_ack));
+fmlarb_dack dack1(.sys_clk(sys_clk), .sys_rst(sys_rst),
+ .stb(m1_stb), .eack((master == 3'd1) & s_eack), .we(m1_we),
+ .stbm(m1_stbm), .ack(m1_ack));
+fmlarb_dack dack2(.sys_clk(sys_clk), .sys_rst(sys_rst),
+ .stb(m2_stb), .eack((master == 3'd2) & s_eack), .we(m2_we),
+ .stbm(m2_stbm), .ack(m2_ack));
+fmlarb_dack dack3(.sys_clk(sys_clk), .sys_rst(sys_rst),
+ .stb(m3_stb), .eack((master == 3'd3) & s_eack), .we(m3_we),
+ .stbm(m3_stbm), .ack(m3_ack));
+fmlarb_dack dack4(.sys_clk(sys_clk), .sys_rst(sys_rst),
+ .stb(m4_stb), .eack((master == 3'd4) & s_eack), .we(m4_we),
+ .stbm(m4_stbm), .ack(m4_ack));
+fmlarb_dack dack5(.sys_clk(sys_clk), .sys_rst(sys_rst),
+ .stb(m5_stb), .eack((master == 3'd5) & s_eack), .we(m5_we),
+ .stbm(m5_stbm), .ack(m5_ack));
+/* Mux data write signals */
reg [2:0] wmaster;
-reg [1:0] burst_counter;
always @(posedge sys_clk) begin
- if(sys_rst) begin
+ if(sys_rst)
wmaster <= 3'd0;
- burst_counter <= 2'd0;
- end else begin
- if(|burst_counter)
- burst_counter <= burst_counter - 2'd1;
- if(write_burst_start)
- burst_counter <= 2'd2;
- if(~write_burst_start & ~(|burst_counter))
- wmaster <= next_master;
- end
+ else if(s_we & s_eack)
+ wmaster <= master;
end
always @(*) begin
View
82 cores/fmlarb/rtl/fmlarb_dack.v
@@ -0,0 +1,82 @@
+/*
+ * Milkymist SoC
+ * Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * Generate ack signal from early ack signal and mask strobe.
+ * After an early acked write, it should pulse after 2 cycles.
+ * After an early acked read, it should pulse after CL+3 cycles, that is
+ * 5 cycles when tim_cas = 0 (assumed here)
+ * 6 cycles when tim_cas = 1
+ */
+
+module fmlarb_dack(
+ input sys_clk,
+ input sys_rst,
+
+ input stb,
+ input eack,
+ input we,
+
+ output stbm,
+ output reg ack
+);
+
+wire read = eack & ~we;
+wire write = eack & we;
+
+reg ack_read2;
+reg ack_read1;
+reg ack_read0;
+
+always @(posedge sys_clk) begin
+ if(sys_rst) begin
+ ack_read2 <= 1'b0;
+ ack_read1 <= 1'b0;
+ ack_read0 <= 1'b0;
+ end else begin
+ ack_read2 <= read;
+ ack_read1 <= ack_read2;
+ ack_read0 <= ack_read1;
+ end
+end
+
+reg ack0;
+always @(posedge sys_clk) begin
+ if(sys_rst) begin
+ ack0 <= 1'b0;
+ ack <= 1'b0;
+ end else begin
+ ack0 <= ack_read0|write;
+ ack <= ack0;
+ end
+end
+
+reg mask;
+assign stbm = stb & ~mask;
+
+always @(posedge sys_clk) begin
+ if(sys_rst)
+ mask <= 1'b0;
+ else begin
+ if(eack)
+ mask <= 1'b1;
+ if(ack)
+ mask <= 1'b0;
+ end
+end
+
+endmodule
View
40 cores/hpdmc_ddr32/rtl/hpdmc.v
@@ -1,6 +1,6 @@
/*
* Milkymist SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
+ * Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -42,7 +42,7 @@ module hpdmc #(
input [sdram_depth-1:0] fml_adr,
input fml_stb,
input fml_we,
- output fml_ack,
+ output fml_eack,
input [7:0] fml_sel,
input [63:0] fml_di,
output [63:0] fml_do,
@@ -162,11 +162,6 @@ hpdmc_ctlif #(
);
/* SDRAM management unit */
-wire mgmt_stb;
-wire mgmt_we;
-wire [sdram_depth-3-1:0] mgmt_address;
-wire mgmt_ack;
-
wire read;
wire write;
wire [3:0] concerned_bank;
@@ -186,10 +181,10 @@ hpdmc_mgmt #(
.tim_refi(tim_refi),
.tim_rfc(tim_rfc),
- .stb(mgmt_stb),
- .we(mgmt_we),
- .address(mgmt_address),
- .ack(mgmt_ack),
+ .stb(fml_stb),
+ .we(fml_we),
+ .address(fml_adr[sdram_depth-1:3]),
+ .ack(fml_eack),
.read(read),
.write(write),
@@ -206,28 +201,6 @@ hpdmc_mgmt #(
.sdram_ba(sdram_ba_mgmt)
);
-/* Bus interface */
-wire data_ack;
-
-hpdmc_busif #(
- .sdram_depth(sdram_depth)
-) busif (
- .sys_clk(sys_clk),
- .sdram_rst(sdram_rst),
-
- .fml_adr(fml_adr),
- .fml_stb(fml_stb),
- .fml_we(fml_we),
- .fml_ack(fml_ack),
-
- .mgmt_stb(mgmt_stb),
- .mgmt_we(mgmt_we),
- .mgmt_address(mgmt_address),
- .mgmt_ack(mgmt_ack),
-
- .data_ack(data_ack)
-);
-
/* Data path controller */
wire direction;
@@ -242,7 +215,6 @@ hpdmc_datactl datactl(
.write_safe(write_safe),
.precharge_safe(precharge_safe),
- .ack(data_ack),
.direction(direction),
.tim_cas(tim_cas),
View
58 cores/hpdmc_ddr32/rtl/hpdmc_busif.v
@@ -1,58 +0,0 @@
-/*
- * Milkymist SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* Simple FML interface for HPDMC */
-
-module hpdmc_busif #(
- parameter sdram_depth = 26
-) (
- input sys_clk,
- input sdram_rst,
-
- input [sdram_depth-1:0] fml_adr,
- input fml_stb,
- input fml_we,
- output fml_ack,
-
- output mgmt_stb,
- output mgmt_we,
- output [sdram_depth-3-1:0] mgmt_address, /* in 64-bit words */
- input mgmt_ack,
-
- input data_ack
-);
-
-reg mgmt_stb_en;
-
-assign mgmt_stb = fml_stb & mgmt_stb_en;
-assign mgmt_we = fml_we;
-assign mgmt_address = fml_adr[sdram_depth-1:3];
-
-assign fml_ack = data_ack;
-
-always @(posedge sys_clk) begin
- if(sdram_rst)
- mgmt_stb_en = 1'b1;
- else begin
- if(mgmt_ack)
- mgmt_stb_en = 1'b0;
- if(data_ack)
- mgmt_stb_en = 1'b1;
- end
-end
-
-endmodule
View
50 cores/hpdmc_ddr32/rtl/hpdmc_datactl.v
@@ -1,6 +1,6 @@
/*
* Milkymist SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
+ * Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -26,7 +26,6 @@ module hpdmc_datactl(
output reg write_safe,
output [3:0] precharge_safe,
- output reg ack,
output reg direction,
output direction_r,
@@ -46,7 +45,7 @@ always @(posedge sys_clk) begin
read_safe <= 1'b1;
end else begin
if(read) begin
- read_safe_counter <= 3'd4;
+ read_safe_counter <= 3'd3;
read_safe <= 1'b0;
end else if(write) begin
/* after a write, read is unsafe for 5 cycles (4 transfers + tWTR=1) */
@@ -76,7 +75,7 @@ always @(posedge sys_clk) begin
write_safe_counter <= {1'b1, tim_cas, ~tim_cas};
write_safe <= 1'b0;
end else if(write) begin
- write_safe_counter <= 3'd3;
+ write_safe_counter <= 3'd4;
write_safe <= 1'b0;
end else begin
if(write_safe_counter == 3'd1)
@@ -87,49 +86,6 @@ always @(posedge sys_clk) begin
end
end
-/* Generate ack signal.
- * After write is asserted, it should pulse after 2 cycles.
- * After read is asserted, it should pulse after CL+3 cycles, that is
- * 5 cycles when tim_cas = 0
- * 6 cycles when tim_cas = 1
- */
-
-reg ack_read3;
-reg ack_read2;
-reg ack_read1;
-reg ack_read0;
-
-always @(posedge sys_clk) begin
- if(sdram_rst) begin
- ack_read3 <= 1'b0;
- ack_read2 <= 1'b0;
- ack_read1 <= 1'b0;
- ack_read0 <= 1'b0;
- end else begin
- if(tim_cas) begin
- ack_read3 <= read;
- ack_read2 <= ack_read3;
- ack_read1 <= ack_read2;
- ack_read0 <= ack_read1;
- end else begin
- ack_read2 <= read;
- ack_read1 <= ack_read2;
- ack_read0 <= ack_read1;
- end
- end
-end
-
-reg ack0;
-always @(posedge sys_clk) begin
- if(sdram_rst) begin
- ack0 <= 1'b0;
- ack <= 1'b0;
- end else begin
- ack0 <= ack_read0|write;
- ack <= ack0;
- end
-end
-
reg [1:0] counter_writedirection;
always @(posedge sys_clk) begin
if(sdram_rst) begin
View
2  cores/hpdmc_ddr32/rtl/hpdmc_mgmt.v
@@ -1,6 +1,6 @@
/*
* Milkymist SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
+ * Copyright (C) 2007, 2008, 2009, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
View
61 cores/hpdmc_ddr32/test/tb_hpdmc.v
@@ -18,9 +18,9 @@
`timescale 1ns / 1ps
`define ENABLE_VCD
-//`define TEST_SOMETRANSFERS
+`define TEST_SOMETRANSFERS
//`define TEST_RANDOMTRANSFERS
-`define TEST_PEAK
+//`define TEST_PEAK
module tb_hpdmc();
@@ -82,7 +82,7 @@ wire [31:0] csr_do;
reg [25:0] fml_adr;
reg fml_stb;
reg fml_we;
-wire fml_ack;
+wire fml_eack;
reg [7:0] fml_sel;
reg [63:0] fml_di;
wire [63:0] fml_do;
@@ -100,7 +100,7 @@ hpdmc dut(
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
- .fml_ack(fml_ack),
+ .fml_eack(fml_eack),
.fml_sel(fml_sel),
.fml_di(fml_di),
.fml_do(fml_do),
@@ -165,23 +165,35 @@ real read_clocks;
task readburst;
input [31:0] address;
integer i;
+integer b;
begin
$display("READ [%x]", address);
fml_adr = address;
fml_stb = 1'b1;
fml_we = 1'b0;
i = 0;
- while(~fml_ack) begin
+ #1;
+ while(~fml_eack) begin
i = i+1;
waitclock;
end
- $display("%t: Memory Read : %x=%x acked in %d clocks", $time, address, fml_do, i);
+ if(i == 0) begin
+ b = 1;
+ waitclock;
+ end else
+ b = 0;
+ $display("%t: Memory Read : %x early acked in %d clocks", $time, address, i);
fml_stb = 1'b0;
reads = reads + 1;
- read_clocks = read_clocks + i;
- for(i=0;i<3;i=i+1) begin
+ read_clocks = read_clocks + i + 5;
+ i = 0;
+ while(i < (4-b)) begin
+ i = i+1;
+ waitclock;
+ end
+ for(i=0;i<4;i=i+1) begin
waitclock;
- $display("%t: (R burst continuing) %x", $time, fml_do);
+ $display("%t: (R burst) %x", $time, fml_do);
end
waitclock;
@@ -194,6 +206,7 @@ real write_clocks;
task writeburst;
input [31:0] address;
integer i;
+integer b;
begin
$display("WRITE [%x]", address);
fml_adr = address;
@@ -202,18 +215,30 @@ begin
fml_sel = 8'hff;
fml_di = {$random, $random};
i = 0;
- while(~fml_ack) begin
+ #1;
+ while(~fml_eack) begin
i = i+1;
waitclock;
end
- $display("%t: Memory Write : %x=%x acked in %d clocks", $time, address, fml_di, i);
+ if(i == 0) begin
+ waitclock;
+ b = 1;
+ end else
+ b = 0;
+
+ $display("%t: Memory Write : %x=%x early acked in %d clocks", $time, address, fml_di, i);
fml_stb = 1'b0;
writes = writes + 1;
- write_clocks = write_clocks + i;
+ write_clocks = write_clocks + i + 2;
+ i = 0;
+ while(i < (2-b)) begin
+ i = i+1;
+ waitclock;
+ end
for(i=0;i<3;i=i+1) begin
waitclock;
fml_di = {$random, $random};
- $display("%t: (W burst continuing) %x", $time, fml_di);
+ $display("%t: (W burst) %x", $time, fml_di);
end
waitclock;
@@ -338,11 +363,13 @@ always begin
* Try some transfers.
*/
writeburst(32'h00);
- writeburst(32'h20);
+ writeburst(32'h200000);
+ //writeburst(32'h20);
//writeburst(32'h40);
+ readburst(32'h200000);
readburst(32'h00);
- readburst(32'h20);
+ //readburst(32'h20);
/*readburst(32'h40);
writeburst(32'h40);
readburst(32'h40);*/
@@ -386,7 +413,7 @@ always begin
n = 0;
while(n < 10) begin
- while(~fml_ack) begin
+ while(~fml_eack) begin
waitclock;
end
waitclock;
@@ -398,7 +425,7 @@ always begin
n = 0;
while(n < 10) begin
- while(~fml_ack) begin
+ while(~fml_eack) begin
waitclock;
end
waitclock;
Please sign in to comment.
Something went wrong with that request. Please try again.