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TMU: make fragment, fetch and commit FIFO sizes configurable at top l…

…evel
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1 parent 64ec831 commit 9460bd9d1d9338a60a4fce3a5d5e04ce16a7a03e @sbourdeauducq sbourdeauducq committed Jul 25, 2011
Showing with 17 additions and 4 deletions.
  1. +7 −1 cores/tmu2/rtl/tmu2.v
  2. +4 −1 cores/tmu2/rtl/tmu2_fetchtexel.v
  3. +6 −2 cores/tmu2/rtl/tmu2_texmem.v
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@@ -18,7 +18,10 @@
module tmu2 #(
parameter csr_addr = 4'h0,
parameter fml_depth = 26,
- parameter texel_cache_depth = 15 /* 32kB cache */
+ parameter texel_cache_depth = 15, /* < 32kB cache */
+ parameter fragq_depth = 5, /* < log2 of the fragment FIFO size */
+ parameter fetchq_depth = 4, /* < log2 of the fetch FIFO size */
+ parameter commitq_depth = 4 /* < log2 of the commit FIFO size */
) (
/* Global clock and reset signals */
input sys_clk,
@@ -614,6 +617,9 @@ wire [5:0] y_frac_f;
tmu2_texmem #(
.cache_depth(texel_cache_depth),
+ .fragq_depth(fragq_depth),
+ .fetchq_depth(fetchq_depth),
+ .commitq_depth(commitq_depth),
.fml_depth(fml_depth)
) texmem (
.sys_clk(sys_clk),
@@ -16,6 +16,7 @@
*/
module tmu2_fetchtexel #(
+ parameter depth = 2,
parameter fml_depth = 26
) (
input sys_clk,
@@ -55,7 +56,9 @@ assign pipe_ack_o = fetch_en & (~fml_stb | fml_ack);
/* Gather received data */
wire fifo_we;
-tmu2_fifo64to256 fifo64to256(
+tmu2_fifo64to256 #(
+ .depth(depth)
+) fifo64to256 (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
@@ -23,6 +23,9 @@
module tmu2_texmem #(
parameter cache_depth = 13, /* < log2 of the capacity in 8-bit words */
+ parameter fragq_depth = 5, /* < log2 of the fragment FIFO size */
+ parameter fetchq_depth = 4, /* < log2 of the fetch FIFO size */
+ parameter commitq_depth = 4, /* < log2 of the commit FIFO size */
parameter fml_depth = 26
) (
input sys_clk,
@@ -232,7 +235,7 @@ wire fragf_miss_d;
tmu2_buffer #(
.width(fml_depth-1+4*cache_depth+2*6+4),
- .depth(4)
+ .depth(fragq_depth)
) frag_fifo (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
@@ -273,7 +276,7 @@ wire fetchf_miss_d;
tmu2_buffer #(
.width(4*(fml_depth-5)+4),
- .depth(3)
+ .depth(fetchq_depth)
) fetch_fifo (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
@@ -332,6 +335,7 @@ wire fetchtexel_pipe_stb;
wire fetchtexel_pipe_ack;
wire [255:0] fetchtexel_dat;
tmu2_fetchtexel #(
+ .depth(commitq_depth),
.fml_depth(fml_depth)
) fetchtexel (
.sys_clk(sys_clk),

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