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TMU prefetch: fix commit FIFO write indexing

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1 parent 7abd367 commit df573f94f9875cf4a2dcee409a6e0f6b83c644be @sbourdeauducq sbourdeauducq committed Jul 26, 2011
Showing with 4 additions and 4 deletions.
  1. +4 −4 cores/tmu2/rtl/tmu2_fifo64to256.v
@@ -57,10 +57,10 @@ always @(posedge sys_clk) begin
if(write) begin
produce <= produce + 1;
case(produce[1:0])
- 2'd0: storage1[produce[3:2]] <= wd;
- 2'd1: storage2[produce[3:2]] <= wd;
- 2'd2: storage3[produce[3:2]] <= wd;
- 2'd3: storage4[produce[3:2]] <= wd;
+ 2'd0: storage1[produce[depth+1:2]] <= wd;
+ 2'd1: storage2[produce[depth+1:2]] <= wd;
+ 2'd2: storage3[produce[depth+1:2]] <= wd;
+ 2'd3: storage4[produce[depth+1:2]] <= wd;
endcase
end
case({read, write})

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