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Do not assert PHY reset for too long

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commit e39899e271a1d1b9e6199eb25faecb65262be8ce 1 parent a026067
@sbourdeauducq sbourdeauducq authored
Showing with 2 additions and 2 deletions.
  1. +2 −2 cores/minimac2/rtl/minimac2_ctlif.v
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4 cores/minimac2/rtl/minimac2_ctlif.v
@@ -56,7 +56,7 @@ always @(posedge sys_clk) begin
end
reg phy_rst;
-assign phy_rst_n = ~phy_rst;
+assign phy_rst_n = ~(phy_rst | sys_rst);
/*
* RX Slots
@@ -81,7 +81,7 @@ always @(posedge sys_clk) begin
mii_data_oe <= 1'b0;
mii_data_do <= 1'b0;
phy_mii_clk <= 1'b0;
- phy_rst <= 1'b1;
+ phy_rst <= 1'b0;
slot0_state <= 2'b00;
slot1_state <= 2'b00;
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