diff --git a/boards/avnet-sp3aevl/rtl/lm32_include.v b/boards/avnet-sp3aevl/rtl/lm32_include.v
deleted file mode 100644
index e33360b3..00000000
--- a/boards/avnet-sp3aevl/rtl/lm32_include.v
+++ /dev/null
@@ -1,356 +0,0 @@
-// =============================================================================
-//                           COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
-//
-// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court                            408-826-6000 (other locations)
-// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
-// U.S.A                                   email: techsupport@latticesemi.com
-// =============================================================================/
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-`ifdef LM32_INCLUDE_V
-`else
-`define LM32_INCLUDE_V
-
-//
-// Common configuration options
-//
-
-`define CFG_EBA_RESET 32'h0
-`define CFG_DEBA_RESET 32'h0
-
-`define CFG_PL_MULTIPLY_ENABLED
-`define CFG_PL_BARREL_SHIFT_ENABLED
-`define CFG_SIGN_EXTEND_ENABLED
-`define CFG_MC_DIVIDE_ENABLED
-
-`define CFG_ICACHE_ENABLED
-`define CFG_ICACHE_ASSOCIATIVITY   2
-`define CFG_ICACHE_SETS            256
-`define CFG_ICACHE_BYTES_PER_LINE  16
-`define CFG_ICACHE_BASE_ADDRESS    32'h0
-`define CFG_ICACHE_LIMIT           32'h7fffffff
-
-//`define CFG_DCACHE_ENABLED
-`define CFG_DCACHE_ASSOCIATIVITY   2
-`define CFG_DCACHE_SETS            512
-`define CFG_DCACHE_BYTES_PER_LINE  16
-`define CFG_DCACHE_BASE_ADDRESS    32'h0
-`define CFG_DCACHE_LIMIT           32'h7fffffff
-
-
-//
-// End of common configuration options
-//
-
-`ifdef TRUE
-`else
-`define TRUE    1'b1
-`define FALSE   1'b0
-`define TRUE_N  1'b0
-`define FALSE_N 1'b1
-`endif
-
-// Wishbone configuration
-`define CFG_IWB_ENABLED
-`define CFG_DWB_ENABLED
-
-// Data-path width
-`define LM32_WORD_WIDTH                 32
-`define LM32_WORD_RNG                   (`LM32_WORD_WIDTH-1):0
-`define LM32_SHIFT_WIDTH                5
-`define LM32_SHIFT_RNG                  (`LM32_SHIFT_WIDTH-1):0
-`define LM32_BYTE_SELECT_WIDTH          4
-`define LM32_BYTE_SELECT_RNG            (`LM32_BYTE_SELECT_WIDTH-1):0
-
-// Register file size
-`define LM32_REGISTERS                  32
-`define LM32_REG_IDX_WIDTH              5
-`define LM32_REG_IDX_RNG                (`LM32_REG_IDX_WIDTH-1):0
-
-// Standard register numbers
-`define LM32_RA_REG                     `LM32_REG_IDX_WIDTH'd29
-`define LM32_EA_REG                     `LM32_REG_IDX_WIDTH'd30
-`define LM32_BA_REG                     `LM32_REG_IDX_WIDTH'd31
-
-// Range of Program Counter. Two LSBs are always 0. 
-// `ifdef CFG_ICACHE_ENABLED
-// `define LM32_PC_WIDTH                   (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2)
-// `else
-// `ifdef CFG_IWB_ENABLED
-`define LM32_PC_WIDTH                   (`LM32_WORD_WIDTH-2)
-// `else
-// `define LM32_PC_WIDTH                   `LM32_IROM_ADDRESS_WIDTH
-// `endif
-// `endif
-`define LM32_PC_RNG                     (`LM32_PC_WIDTH+2-1):2
-
-// Range of an instruction
-`define LM32_INSTRUCTION_WIDTH          32
-`define LM32_INSTRUCTION_RNG            (`LM32_INSTRUCTION_WIDTH-1):0
-
-// Adder operation
-`define LM32_ADDER_OP_ADD               1'b0
-`define LM32_ADDER_OP_SUBTRACT          1'b1
-
-// Shift direction
-`define LM32_SHIFT_OP_RIGHT             1'b0
-`define LM32_SHIFT_OP_LEFT              1'b1
-
-// Currently always enabled
-`define CFG_BUS_ERRORS_ENABLED
-
-// Derive macro that indicates whether we have single-stepping or not
-`ifdef CFG_ROM_DEBUG_ENABLED
-`define LM32_SINGLE_STEP_ENABLED
-`else
-`ifdef CFG_HW_DEBUG_ENABLED
-`define LM32_SINGLE_STEP_ENABLED
-`endif
-`endif
-
-// Derive macro that indicates whether JTAG interface is required
-`ifdef CFG_JTAG_UART_ENABLED
-`define LM32_JTAG_ENABLED
-`else
-`ifdef CFG_DEBUG_ENABLED
-`define LM32_JTAG_ENABLED
-`else
-`endif
-`endif
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-`ifdef CFG_PL_BARREL_SHIFT_ENABLED
-`define LM32_BARREL_SHIFT_ENABLED
-`else // CFG_PL_BARREL_SHIFT_ENABLED
-`ifdef CFG_MC_BARREL_SHIFT_ENABLED
-`define LM32_BARREL_SHIFT_ENABLED
-`else
-`define LM32_NO_BARREL_SHIFT
-`endif
-`endif // CFG_PL_BARREL_SHIFT_ENABLED
-
-// Derive macro that indicates whether we have a multiplier or not
-`ifdef CFG_PL_MULTIPLY_ENABLED
-`define LM32_MULTIPLY_ENABLED
-`else
-`ifdef CFG_MC_MULTIPLY_ENABLED
-`define LM32_MULTIPLY_ENABLED
-`endif
-`endif
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-`ifdef CFG_MC_DIVIDE_ENABLED
-`define LM32_MC_ARITHMETIC_ENABLED
-`endif
-`ifdef CFG_MC_MULTIPLY_ENABLED
-`define LM32_MC_ARITHMETIC_ENABLED
-`endif
-`ifdef CFG_MC_BARREL_SHIFT_ENABLED
-`define LM32_MC_ARITHMETIC_ENABLED
-`endif
-
-// Derive macro that indicates if we are using an EBR register file
-`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
-`define LM32_EBR_REGISTER_FILE
-`endif
-`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
-`define LM32_EBR_REGISTER_FILE
-`endif
-
-// Revision number
-`define LM32_REVISION                   6'h02
-
-// Logical operations - Function encoded directly in instruction
-`define LM32_LOGIC_OP_RNG               3:0
-
-// Conditions for conditional branches
-`define LM32_CONDITION_WIDTH            3
-`define LM32_CONDITION_RNG              (`LM32_CONDITION_WIDTH-1):0
-`define LM32_CONDITION_E                3'b001
-`define LM32_CONDITION_G                3'b010
-`define LM32_CONDITION_GE               3'b011
-`define LM32_CONDITION_GEU              3'b100
-`define LM32_CONDITION_GU               3'b101
-`define LM32_CONDITION_NE               3'b111
-`define LM32_CONDITION_U1               3'b000
-`define LM32_CONDITION_U2               3'b110
-
-// Size of load or store instruction - Encoding corresponds to opcode
-`define LM32_SIZE_WIDTH                 2
-`define LM32_SIZE_RNG                   1:0
-`define LM32_SIZE_BYTE                  2'b00
-`define LM32_SIZE_HWORD                 2'b11
-`define LM32_SIZE_WORD                  2'b10
-`define LM32_ADDRESS_LSBS_WIDTH         2
-
-// Width and range of a CSR index
-`ifdef CFG_DEBUG_ENABLED
-`define LM32_CSR_WIDTH                  5
-`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
-`else
-`ifdef CFG_JTAG_ENABLED
-`define LM32_CSR_WIDTH                  4
-`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
-`else
-`define LM32_CSR_WIDTH                  3
-`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
-`endif
-`endif
-
-// CSR indices
-`define LM32_CSR_IE                     `LM32_CSR_WIDTH'h0
-`define LM32_CSR_IM                     `LM32_CSR_WIDTH'h1
-`define LM32_CSR_IP                     `LM32_CSR_WIDTH'h2
-`define LM32_CSR_ICC                    `LM32_CSR_WIDTH'h3
-`define LM32_CSR_DCC                    `LM32_CSR_WIDTH'h4
-`define LM32_CSR_CC                     `LM32_CSR_WIDTH'h5
-`define LM32_CSR_CFG                    `LM32_CSR_WIDTH'h6
-`define LM32_CSR_EBA                    `LM32_CSR_WIDTH'h7
-`ifdef CFG_DEBUG_ENABLED
-`define LM32_CSR_DC                     `LM32_CSR_WIDTH'h8
-`define LM32_CSR_DEBA                   `LM32_CSR_WIDTH'h9
-`endif
-`define LM32_CSR_CFG2                   `LM32_CSR_WIDTH'ha
-`ifdef CFG_JTAG_ENABLED
-`define LM32_CSR_JTX                    `LM32_CSR_WIDTH'he
-`define LM32_CSR_JRX                    `LM32_CSR_WIDTH'hf
-`endif
-`ifdef CFG_DEBUG_ENABLED
-`define LM32_CSR_BP0                    `LM32_CSR_WIDTH'h10
-`define LM32_CSR_BP1                    `LM32_CSR_WIDTH'h11
-`define LM32_CSR_BP2                    `LM32_CSR_WIDTH'h12
-`define LM32_CSR_BP3                    `LM32_CSR_WIDTH'h13
-`define LM32_CSR_WP0                    `LM32_CSR_WIDTH'h18
-`define LM32_CSR_WP1                    `LM32_CSR_WIDTH'h19
-`define LM32_CSR_WP2                    `LM32_CSR_WIDTH'h1a
-`define LM32_CSR_WP3                    `LM32_CSR_WIDTH'h1b
-`endif 
-
-// Values for WPC CSR
-`define LM32_WPC_C_RNG                  1:0
-`define LM32_WPC_C_DISABLED             2'b00
-`define LM32_WPC_C_READ                 2'b01
-`define LM32_WPC_C_WRITE                2'b10
-`define LM32_WPC_C_READ_WRITE           2'b11
-
-// Exception IDs
-`define LM32_EID_WIDTH                  3
-`define LM32_EID_RNG                    (`LM32_EID_WIDTH-1):0
-`define LM32_EID_RESET                  3'h0
-`define LM32_EID_BREAKPOINT             3'd1
-`define LM32_EID_INST_BUS_ERROR         3'h2
-`define LM32_EID_WATCHPOINT             3'd3
-`define LM32_EID_DATA_BUS_ERROR         3'h4
-`define LM32_EID_DIVIDE_BY_ZERO         3'h5
-`define LM32_EID_INTERRUPT              3'h6
-`define LM32_EID_SCALL                  3'h7
-
-// Pipeline result selection mux controls
-
-`define LM32_D_RESULT_SEL_0_RNG          0:0
-`define LM32_D_RESULT_SEL_0_REG_0        1'b0
-`define LM32_D_RESULT_SEL_0_NEXT_PC      1'b1
-
-`define LM32_D_RESULT_SEL_1_RNG          1:0
-`define LM32_D_RESULT_SEL_1_ZERO         2'b00
-`define LM32_D_RESULT_SEL_1_REG_1        2'b01
-`define LM32_D_RESULT_SEL_1_IMMEDIATE    2'b10
-
-`define LM32_USER_OPCODE_WIDTH           11
-`define LM32_USER_OPCODE_RNG             (`LM32_USER_OPCODE_WIDTH-1):0
-
-// Derive a macro to indicate if either of the caches are implemented
-`ifdef CFG_ICACHE_ENABLED
-`define LM32_CACHE_ENABLED
-`else
-`ifdef CFG_DCACHE_ENABLED
-`define LM32_CACHE_ENABLED
-`endif
-`endif
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-`define CFG_INTERRUPTS_ENABLED
-
-// Currently this is fixed to 32 and should not be changed
-`define CFG_INTERRUPTS                  32
-`define LM32_INTERRUPT_WIDTH            `CFG_INTERRUPTS
-`define LM32_INTERRUPT_RNG              (`LM32_INTERRUPT_WIDTH-1):0
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-`define LM32_BYTE_WIDTH                 8
-`define LM32_BYTE_RNG                   7:0
-`define LM32_HWORD_WIDTH                16
-`define LM32_HWORD_RNG                  15:0
-
-// Word sub-byte indicies
-`define LM32_BYTE_0_RNG                  7:0
-`define LM32_BYTE_1_RNG                  15:8
-`define LM32_BYTE_2_RNG                  23:16
-`define LM32_BYTE_3_RNG                  31:24
-
-// Word sub-halfword indices
-`define LM32_HWORD_0_RNG                 15:0
-`define LM32_HWORD_1_RNG                 31:16
-
-// Use a synchronous reset
-`define CFG_RESET_SENSITIVITY
-
-// V.T. Srce
-`define SRCE
-
-// Whether to include context registers for debug exceptions
-// in addition to standard exception handling registers
-// Bizarre - Removing this increases LUT count!
-`define CFG_DEBUG_EXCEPTIONS_ENABLED
-
-// Wishbone defines 
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-`define LM32_CTYPE_WIDTH                3
-`define LM32_CTYPE_RNG                  (`LM32_CTYPE_WIDTH-1):0
-`define LM32_CTYPE_CLASSIC              3'b000
-`define LM32_CTYPE_CONSTANT             3'b001
-`define LM32_CTYPE_INCREMENTING         3'b010
-`define LM32_CTYPE_END                  3'b111
-
-// Wishbone burst types
-`define LM32_BTYPE_WIDTH                2
-`define LM32_BTYPE_RNG                  (`LM32_BTYPE_WIDTH-1):0
-`define LM32_BTYPE_LINEAR               2'b00
-`define LM32_BTYPE_4_BEAT               2'b01
-`define LM32_BTYPE_8_BEAT               2'b10
-`define LM32_BTYPE_16_BEAT              2'b11
-
-`endif
diff --git a/boards/avnet-sp3aevl/rtl/setup.v b/boards/avnet-sp3aevl/rtl/setup.v
deleted file mode 100644
index ebded551..00000000
--- a/boards/avnet-sp3aevl/rtl/setup.v
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Milkymist VJ SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-/*
- * System clock frequency in Hz.
- */
-`define CLOCK_FREQUENCY 64000000
-
-/*
- * System clock period in ns (must be in sync with CLOCK_FREQUENCY).
- */
-`define CLOCK_PERIOD 15.625
-
-/*
- * Default baudrate for the debug UART.
- */
-`define BAUD_RATE 115200
diff --git a/boards/avnet-sp3aevl/rtl/system.v b/boards/avnet-sp3aevl/rtl/system.v
deleted file mode 100644
index 178cfb17..00000000
--- a/boards/avnet-sp3aevl/rtl/system.v
+++ /dev/null
@@ -1,519 +0,0 @@
-/*
- * Milkymist VJ SoC
- * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-`include "setup.v"
-
-module system(
-	input clkin,
-	input resetin,
-	
-	// Boot ROM
-	output [21:0] flash_adr,
-	input [7:0] flash_d,
-	output flash_byte_n,
-	output flash_oe_n,
-	output flash_we_n,
-	output flash_ce_n,
-	output flash_reset_n,
-
-	// UART
-	input uart_rxd,
-	output uart_txd,
-
-	// GPIO
-	input [2:0] btn,    // 3
-	output [3:0] led    //        2 (2 LEDs for UART activity)
-);
-
-//------------------------------------------------------------------
-// Clock and Reset Generation
-//------------------------------------------------------------------
-wire sys_clk;
-wire hard_reset;
-
-`ifndef SIMULATION
-DCM_SP #(
-	.CLKDV_DIVIDE(1.5), // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-
-	.CLKFX_DIVIDE(1), // 1 to 32
-	.CLKFX_MULTIPLY(4), // 2 to 32
-
-	.CLKIN_DIVIDE_BY_2("FALSE"),
-	.CLKIN_PERIOD(62.5),
-	.CLKOUT_PHASE_SHIFT("NONE"),
-	.CLK_FEEDBACK("NONE"),
-	.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
-	.DFS_FREQUENCY_MODE("LOW"),
-	.DLL_FREQUENCY_MODE("LOW"),
-	.DUTY_CYCLE_CORRECTION("TRUE"),
-	.FACTORY_JF(16'hF0F0),
-	.PHASE_SHIFT(0),
-	.STARTUP_WAIT("TRUE")
-) clkgen (
-	.CLK0(),
-	.CLK90(),
-	.CLK180(),
-	.CLK270(),
-
-	.CLK2X(),
-	.CLK2X180(),
-
-	.CLKDV(),
-	.CLKFX(sys_clk),
-	.CLKFX180(),
-	.LOCKED(),
-	.CLKFB(),
-	.CLKIN(clkin),
-	.RST(1'b0)
-);
-`else
-assign sys_clk = clkin;
-`endif
-
-`ifndef SIMULATION
-/* Synchronize the reset input */
-reg rst0;
-reg rst1;
-always @(posedge sys_clk) rst0 <= resetin;
-always @(posedge sys_clk) rst1 <= rst0;
-
-/* Debounce it
- * and generate power-on reset.
- */
-reg [19:0] rst_debounce;
-reg sys_rst;
-initial rst_debounce <= 20'hFFFFF;
-initial sys_rst <= 1'b1;
-always @(posedge sys_clk) begin
-	if(rst1 | hard_reset)
-		rst_debounce <= 20'hFFFFF;
-	else if(rst_debounce != 20'd0)
-		rst_debounce <= rst_debounce - 20'd1;
-	sys_rst <= rst_debounce != 20'd0;
-end
-
-/*
- * We must release the Flash reset before the system reset
- * because the Flash needs some time to come out of reset
- * and the CPU begins fetching instructions from it
- * as soon as the system reset is released.
- * From datasheet, minimum reset pulse width is 100ns
- * and reset-to-read time is 150ns.
- */
-
-reg [7:0] flash_rstcounter;
-initial flash_rstcounter <= 8'd0;
-always @(posedge sys_clk) begin
-	if(~sys_rst)
-		flash_rstcounter <= 8'd0;
-	else if(~flash_rstcounter[7])
-		flash_rstcounter <= flash_rstcounter + 8'd1;
-end
-
-assign flash_reset_n = ~flash_rstcounter[7];
-
-`else
-wire sys_rst;
-assign sys_rst = resetin;
-`endif
-
-//------------------------------------------------------------------
-// Wishbone master wires
-//------------------------------------------------------------------
-wire [31:0]	cpuibus_adr,
-		cpudbus_adr;
-
-wire [2:0]	cpuibus_cti,
-		cpudbus_cti;
-
-wire [31:0]	cpuibus_dat_r,
-		cpudbus_dat_r,
-		cpudbus_dat_w;
-
-wire [3:0]	cpudbus_sel;
-
-wire		cpudbus_we;
-
-wire		cpuibus_cyc,
-		cpudbus_cyc;
-
-wire		cpuibus_stb,
-		cpudbus_stb;
-
-wire		cpuibus_ack,
-		cpudbus_ack;
-
-//------------------------------------------------------------------
-// Wishbone slave wires
-//------------------------------------------------------------------
-wire [31:0]	brg_adr,
-		norflash_adr,
-		bram_adr,
-		csrbrg_adr;
-
-wire [2:0]	brg_cti,
-		bram_cti;
-
-wire [31:0]	norflash_dat_r,
-		bram_dat_r,
-		bram_dat_w,
-		csrbrg_dat_r,
-		csrbrg_dat_w;
-
-wire [3:0]	bram_sel;
-
-wire		bram_we,
-		csrbrg_we,
-		aceusb_we;
-
-wire		norflash_cyc,
-		bram_cyc,
-		csrbrg_cyc;
-
-wire		norflash_stb,
-		bram_stb,
-		csrbrg_stb;
-
-wire		norflash_ack,
-		bram_ack,
-		csrbrg_ack;
-
-//---------------------------------------------------------------------------
-// Wishbone switch
-//---------------------------------------------------------------------------
-conbus #(
-	.s_addr_w(3),
-	.s0_addr(3'b000),	// norflash	0x00000000
-	.s1_addr(3'b001),	// bram		0x20000000
-	.s2_addr(3'b010),	// free		0x40000000
-	.s3_addr(3'b100),	// CSR bridge	0x80000000
-	.s4_addr(3'b101)	// free		0xa0000000
-) conbus (
-	.sys_clk(sys_clk),
-	.sys_rst(sys_rst),
-
-	// Master 0
-	.m0_dat_i(32'hx),
-	.m0_dat_o(cpuibus_dat_r),
-	.m0_adr_i(cpuibus_adr),
-	.m0_cti_i(cpuibus_cti),
-	.m0_we_i(1'b0),
-	.m0_sel_i(4'hf),
-	.m0_cyc_i(cpuibus_cyc),
-	.m0_stb_i(cpuibus_stb),
-	.m0_ack_o(cpuibus_ack),
-	// Master 1
-	.m1_dat_i(cpudbus_dat_w),
-	.m1_dat_o(cpudbus_dat_r),
-	.m1_adr_i(cpudbus_adr),
-	.m1_cti_i(cpudbus_cti),
-	.m1_we_i(cpudbus_we),
-	.m1_sel_i(cpudbus_sel),
-	.m1_cyc_i(cpudbus_cyc),
-	.m1_stb_i(cpudbus_stb),
-	.m1_ack_o(cpudbus_ack),
-	// Master 2
-	.m2_dat_i(32'bx),
-	.m2_dat_o(),
-	.m2_adr_i(32'bx),
-	.m2_cti_i(3'bx),
-	.m2_we_i(1'bx),
-	.m2_sel_i(4'bx),
-	.m2_cyc_i(1'b0),
-	.m2_stb_i(1'b0),
-	.m2_ack_o(),
-	// Master 3
-	.m3_dat_i(32'bx),
-	.m3_dat_o(),
-	.m3_adr_i(32'bx),
-	.m3_cti_i(3'bx),
-	.m3_we_i(1'bx),
-	.m3_sel_i(4'bx),
-	.m3_cyc_i(1'b0),
-	.m3_stb_i(1'b0),
-	.m3_ack_o(),
-	// Master 4
-	.m4_dat_i(32'bx),
-	.m4_dat_o(),
-	.m4_adr_i(32'bx),
-	.m4_cti_i(3'bx),
-	.m4_we_i(1'bx),
-	.m4_sel_i(4'bx),
-	.m4_cyc_i(1'b0),
-	.m4_stb_i(1'b0),
-	.m4_ack_o(),
-
-	// Slave 0
-	.s0_dat_i(norflash_dat_r),
-	.s0_adr_o(norflash_adr),
-	.s0_cyc_o(norflash_cyc),
-	.s0_stb_o(norflash_stb),
-	.s0_ack_i(norflash_ack),
-	// Slave 1
-	.s1_dat_i(bram_dat_r),
-	.s1_dat_o(bram_dat_w),
-	.s1_adr_o(bram_adr),
-	.s1_cti_o(bram_cti),
-	.s1_sel_o(bram_sel),
-	.s1_we_o(bram_we),
-	.s1_cyc_o(bram_cyc),
-	.s1_stb_o(bram_stb),
-	.s1_ack_i(bram_ack),
-	// Slave 2
-	.s2_dat_i(32'bx),
-	.s2_dat_o(),
-	.s2_adr_o(),
-	.s2_cti_o(),
-	.s2_sel_o(),
-	.s2_we_o(),
-	.s2_cyc_o(),
-	.s2_stb_o(),
-	.s2_ack_i(1'b0),
-	// Slave 3
-	.s3_dat_i(csrbrg_dat_r),
-	.s3_dat_o(csrbrg_dat_w),
-	.s3_adr_o(csrbrg_adr),
-	.s3_we_o(csrbrg_we),
-	.s3_cyc_o(csrbrg_cyc),
-	.s3_stb_o(csrbrg_stb),
-	.s3_ack_i(csrbrg_ack),
-	// Slave 4
-	.s4_dat_i(32'bx),
-	.s4_dat_o(),
-	.s4_adr_o(),
-	.s4_we_o(),
-	.s4_cyc_o(),
-	.s4_stb_o(),
-	.s4_ack_i(1'b0)
-);
-
-//------------------------------------------------------------------
-// CSR bus
-//------------------------------------------------------------------
-wire [13:0]	csr_a;
-wire		csr_we;
-wire [31:0]	csr_dw;
-wire [31:0]	csr_dr_uart,
-		csr_dr_sysctl;
-
-//---------------------------------------------------------------------------
-// WISHBONE to CSR bridge
-//---------------------------------------------------------------------------
-csrbrg csrbrg(
-	.sys_clk(sys_clk),
-	.sys_rst(sys_rst),
-	
-	.wb_adr_i(csrbrg_adr),
-	.wb_dat_i(csrbrg_dat_w),
-	.wb_dat_o(csrbrg_dat_r),
-	.wb_cyc_i(csrbrg_cyc),
-	.wb_stb_i(csrbrg_stb),
-	.wb_we_i(csrbrg_we),
-	.wb_ack_o(csrbrg_ack),
-	
-	.csr_a(csr_a),
-	.csr_we(csr_we),
-	.csr_do(csr_dw),
-	/* combine all slave->master data lines with an OR */
-	.csr_di(
-		 csr_dr_uart
-		|csr_dr_sysctl
-	)
-);
-
-//---------------------------------------------------------------------------
-// Interrupts
-//---------------------------------------------------------------------------
-wire gpio_irq;
-wire timer0_irq;
-wire timer1_irq;
-wire uartrx_irq;
-wire uarttx_irq;
-
-wire [31:0] cpu_interrupt;
-assign cpu_interrupt = {27'd0,
-	uarttx_irq,
-	uartrx_irq,
-	timer1_irq,
-	timer0_irq,
-	gpio_irq
-};
-
-//---------------------------------------------------------------------------
-// LM32 CPU
-//---------------------------------------------------------------------------
-lm32_top cpu(
-	.clk_i(sys_clk),
-	.rst_i(sys_rst),
-	.interrupt(cpu_interrupt),
-
-	.I_ADR_O(cpuibus_adr),
-	.I_DAT_I(cpuibus_dat_r),
-	.I_DAT_O(),
-	.I_SEL_O(),
-	.I_CYC_O(cpuibus_cyc),
-	.I_STB_O(cpuibus_stb),
-	.I_ACK_I(cpuibus_ack),
-	.I_WE_O(),
-	.I_CTI_O(cpuibus_cti),
-	.I_LOCK_O(),
-	.I_BTE_O(),
-	.I_ERR_I(1'b0),
-	.I_RTY_I(1'b0),
-
-	.D_ADR_O(cpudbus_adr),
-	.D_DAT_I(cpudbus_dat_r),
-	.D_DAT_O(cpudbus_dat_w),
-	.D_SEL_O(cpudbus_sel),
-	.D_CYC_O(cpudbus_cyc),
-	.D_STB_O(cpudbus_stb),
-	.D_ACK_I(cpudbus_ack),
-	.D_WE_O (cpudbus_we),
-	.D_CTI_O(cpudbus_cti),
-	.D_LOCK_O(),
-	.D_BTE_O(),
-	.D_ERR_I(1'b0),
-	.D_RTY_I(1'b0)
-);
-
-//---------------------------------------------------------------------------
-// Boot ROM
-//---------------------------------------------------------------------------
-norflash8 #(
-	.adr_width(22),
-	.swapbytes(1'b1)
-) norflash (
-	.sys_clk(sys_clk),
-	.sys_rst(sys_rst),
-
-	.wb_adr_i(norflash_adr),
-	.wb_dat_o(norflash_dat_r),
-	.wb_stb_i(norflash_stb),
-	.wb_cyc_i(norflash_cyc),
-	.wb_ack_o(norflash_ack),
-	
-	.flash_adr(flash_adr),
-	.flash_d(flash_d)
-);
-
-assign flash_byte_n = 1'b0;
-assign flash_oe_n = 1'b0;
-assign flash_we_n = 1'b1;
-assign flash_ce_n = 1'b0;
-
-//---------------------------------------------------------------------------
-// BRAM
-//---------------------------------------------------------------------------
-//
-// On this board, we have 16k of SRAM instead of 4k
-// so that we have space for loading some programs.
-//
-bram #(
-	.adr_width(14)
-) bram (
-	.sys_clk(sys_clk),
-	.sys_rst(sys_rst),
-
-	.wb_adr_i(bram_adr),
-	.wb_dat_o(bram_dat_r),
-	.wb_dat_i(bram_dat_w),
-	.wb_sel_i(bram_sel),
-	.wb_stb_i(bram_stb),
-	.wb_cyc_i(bram_cyc),
-	.wb_ack_o(bram_ack),
-	.wb_we_i(bram_we)
-);
-
-//---------------------------------------------------------------------------
-// UART
-//---------------------------------------------------------------------------
-uart #(
-	.csr_addr(4'h0),
-	.clk_freq(`CLOCK_FREQUENCY),
-	.baud(`BAUD_RATE)
-) uart (
-	.sys_clk(sys_clk),
-	.sys_rst(sys_rst),
-
-	.csr_a(csr_a),
-	.csr_we(csr_we),
-	.csr_di(csr_dw),
-	.csr_do(csr_dr_uart),
-	
-	.rx_irq(uartrx_irq),
-	.tx_irq(uarttx_irq),
-	
-	.uart_rxd(uart_rxd),
-	.uart_txd(uart_txd)
-);
-
-/* LED0 and LED1 are used as TX/RX indicators.
- * Generate long pulses so we have time to see them
- */
-reg [18:0] rxcounter;
-reg rxled;
-always @(posedge sys_clk) begin
-	if(~uart_rxd)
-		rxcounter <= {19{1'b1}};
-	else if(rxcounter != 19'd0)
-		rxcounter <= rxcounter - 19'd1;
-	rxled <= rxcounter != 19'd0;
-end
-
-reg [18:0] txcounter;
-reg txled;
-always @(posedge sys_clk) begin
-	if(~uart_txd)
-		txcounter <= {19{1'b1}};
-	else if(txcounter != 19'd0)
-		txcounter <= txcounter - 19'd1;
-	txled <= txcounter != 19'd0;
-end
-
-assign led[0] = txled;
-assign led[1] = rxled;
-
-//---------------------------------------------------------------------------
-// System Controller
-//---------------------------------------------------------------------------
-wire [13:0] gpio_outputs;
-
-sysctl #(
-	.csr_addr(4'h1),
-	.ninputs(3),
-	.noutputs(2),
-	.systemid(32'h53334145) /* S3AE */
-) sysctl (
-	.sys_clk(sys_clk),
-	.sys_rst(sys_rst),
-
-	.gpio_irq(gpio_irq),
-	.timer0_irq(timer0_irq),
-	.timer1_irq(timer1_irq),
-
-	.csr_a(csr_a),
-	.csr_we(csr_we),
-	.csr_di(csr_dw),
-	.csr_do(csr_dr_sysctl),
-
-	.gpio_inputs(btn),
-	.gpio_outputs(led[3:2]), /* LED0 and LED1 are used as TX/RX indicators */
-
-	.hard_reset(hard_reset)
-);
-
-endmodule
diff --git a/boards/avnet-sp3aevl/sources.mak b/boards/avnet-sp3aevl/sources.mak
deleted file mode 100644
index 797628ad..00000000
--- a/boards/avnet-sp3aevl/sources.mak
+++ /dev/null
@@ -1,26 +0,0 @@
-BOARD_SRC=$(wildcard $(BOARD_DIR)/*.v)
-
-CONBUS_SRC=$(wildcard $(CORES_DIR)/conbus/rtl/*.v)
-LM32_SRC=						\
-	$(CORES_DIR)/lm32/rtl/lm32_cpu.v		\
-	$(CORES_DIR)/lm32/rtl/lm32_instruction_unit.v	\
-	$(CORES_DIR)/lm32/rtl/lm32_decoder.v		\
-	$(CORES_DIR)/lm32/rtl/lm32_load_store_unit.v	\
-	$(CORES_DIR)/lm32/rtl/lm32_adder.v		\
-	$(CORES_DIR)/lm32/rtl/lm32_addsub.v		\
-	$(CORES_DIR)/lm32/rtl/lm32_logic_op.v		\
-	$(CORES_DIR)/lm32/rtl/lm32_shifter.v		\
-	$(CORES_DIR)/lm32/rtl/lm32_multiplier.v		\
-	$(CORES_DIR)/lm32/rtl/lm32_mc_arithmetic.v	\
-	$(CORES_DIR)/lm32/rtl/lm32_interrupt.v		\
-	$(CORES_DIR)/lm32/rtl/lm32_ram.v		\
-	$(CORES_DIR)/lm32/rtl/lm32_icache.v		\
-	$(CORES_DIR)/lm32/rtl/lm32_dcache.v		\
-	$(CORES_DIR)/lm32/rtl/lm32_top.v
-CSRBRG_SRC=$(wildcard $(CORES_DIR)/csrbrg/rtl/*.v)
-NORFLASH_SRC=$(wildcard $(CORES_DIR)/norflash8/rtl/*.v)
-BRAM_SRC=$(wildcard $(CORES_DIR)/bram/rtl/*.v)
-UART_SRC=$(wildcard $(CORES_DIR)/uart/rtl/*.v)
-SYSCTL_SRC=$(wildcard $(CORES_DIR)/sysctl/rtl/*.v)
-
-CORES_SRC=$(CONBUS_SRC) $(LM32_SRC) $(CSRBRG_SRC) $(NORFLASH_SRC) $(BRAM_SRC) $(UART_SRC) $(SYSCTL_SRC)
diff --git a/boards/avnet-sp3aevl/synthesis/Makefile.xst b/boards/avnet-sp3aevl/synthesis/Makefile.xst
deleted file mode 100644
index 460182ce..00000000
--- a/boards/avnet-sp3aevl/synthesis/Makefile.xst
+++ /dev/null
@@ -1,25 +0,0 @@
-BOARD_DIR=../rtl
-CORES_DIR=../../../cores
-
-include ../sources.mak
-SRC=$(BOARD_SRC) $(CORES_SRC)
-
-all: build/system.bit
-
-build/system.ucf: common.ucf xst.ucf
-	cat common.ucf xst.ucf > build/system.ucf
-
-build/system.prj: $(SRC)
-	rm -f build/system.prj
-	for i in `echo $^`; do \
-	    echo "verilog work ../$$i" >> build/system.prj; \
-	done
-
-build/system.ngc: build/system.prj
-	cd build && xst -ifn ../system.xst
-
-build/system.ngd: build/system.ngc build/system.ucf
-	cd build && ngdbuild -uc system.ucf system.ngc
-
-include common.mak
-
diff --git a/boards/avnet-sp3aevl/synthesis/build/.keep_me b/boards/avnet-sp3aevl/synthesis/build/.keep_me
deleted file mode 100644
index e69de29b..00000000
diff --git a/boards/avnet-sp3aevl/synthesis/common.mak b/boards/avnet-sp3aevl/synthesis/common.mak
deleted file mode 100644
index 7f544178..00000000
--- a/boards/avnet-sp3aevl/synthesis/common.mak
+++ /dev/null
@@ -1,29 +0,0 @@
-prom: build/system.mcs
-
-timing: build/system-routed.twr
-
-usage: build/system-routed.xdl
-	../../../tools/xdlanalyze.pl build/system-routed.xdl 0
-
-load: build/system.bit
-	cd build && impact -batch ../load.cmd
-
-build/system.ncd: build/system.ngd
-	cd build && map system.ngd
-
-build/system-routed.ncd: build/system.ncd
-	cd build && par -ol high -xe n -w system.ncd system-routed.ncd
-
-build/system.bit: build/system-routed.ncd
-	cd build && bitgen -w system-routed.ncd system.bit
-
-build/system-routed.xdl: build/system-routed.ncd
-	cd build && xdl -ncd2xdl system-routed.ncd system-routed.xdl
-
-build/system-routed.twr: build/system-routed.ncd
-	cd build && trce -v 10 system-routed.ncd system.pcf
-
-clean:
-	rm -rf build/*
-
-.PHONY: prom timing usage load clean
diff --git a/boards/avnet-sp3aevl/synthesis/common.ucf b/boards/avnet-sp3aevl/synthesis/common.ucf
deleted file mode 100644
index 60f9568d..00000000
--- a/boards/avnet-sp3aevl/synthesis/common.ucf
+++ /dev/null
@@ -1,69 +0,0 @@
-CONFIG VCCAUX = "3.3";
-
-# ==== Clock input ====
-NET "clkin" TNM_NET = CLK_16MHZ;
-TIMESPEC TS_CLK_16MHZ = PERIOD CLK_16MHZ 62.50 ns;
-
-NET "clkin" LOC = C10 | IOSTANDARD = LVCMOS33;
-
-# ==== Reset button ====
-NET "resetin" LOC = H4 | IOSTANDARD = LVCMOS33;
-
-# ==== Linear Flash ====
-NET "flash_adr(0)" LOC = P16 | IOSTANDARD = LVCMOS33; # also D15
-NET "flash_adr(1)" LOC = N16 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(2)" LOC = L13 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(3)" LOC = K13 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(4)" LOC = M15 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(5)" LOC = M16 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(6)" LOC = L14 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(7)" LOC = L16 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(8)" LOC = J12 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(9)" LOC = J13 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(10)" LOC = G16 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(11)" LOC = F16 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(12)" LOC = H13 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(13)" LOC = G14 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(14)" LOC = E16 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(15)" LOC = F15 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(16)" LOC = G13 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(17)" LOC = F14 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(18)" LOC = E14 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(19)" LOC = F13 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(20)" LOC = D16 | IOSTANDARD = LVCMOS33;
-NET "flash_adr(21)" LOC = D15 | IOSTANDARD = LVCMOS33;
-NET "flash_d(0)" LOC = T14 | IOSTANDARD = LVCMOS33;
-NET "flash_d(1)" LOC = R13 | IOSTANDARD = LVCMOS33;
-NET "flash_d(2)" LOC = T13 | IOSTANDARD = LVCMOS33;
-NET "flash_d(3)" LOC = P12 | IOSTANDARD = LVCMOS33;
-NET "flash_d(4)" LOC = N8 | IOSTANDARD = LVCMOS33;
-NET "flash_d(5)" LOC = P7 | IOSTANDARD = LVCMOS33;
-NET "flash_d(6)" LOC = T6 | IOSTANDARD = LVCMOS33;
-NET "flash_d(7)" LOC = T5 | IOSTANDARD = LVCMOS33;
-NET "flash_byte_n" LOC = N14 | IOSTANDARD = LVCMOS33;
-NET "flash_oe_n" LOC = R15 | IOSTANDARD = LVCMOS33;
-NET "flash_we_n" LOC = N13 | IOSTANDARD = LVCMOS33;
-NET "flash_ce_n" LOC = P15 | IOSTANDARD = LVCMOS33;
-NET "flash_reset_n" LOC = T10 | IOSTANDARD = LVCMOS33;
-
-# ==== UART ====
-NET "uart_txd" LOC = B3 | IOSTANDARD = LVCMOS33;
-NET "uart_rxd" LOC = A3 | IOSTANDARD = LVCMOS33;
-
-# ==== Push buttons ====
-NET "btn(0)" LOC = K3 | IOSTANDARD = LVCMOS33;
-NET "btn(1)" LOC = H5 | IOSTANDARD = LVCMOS33;
-NET "btn(2)" LOC = L3 | IOSTANDARD = LVCMOS33;
-
-# ==== LEDs ====
-NET "led(0)" LOC = D14 | IOSTANDARD = LVCMOS33;
-NET "led(1)" LOC = C16 | IOSTANDARD = LVCMOS33;
-NET "led(2)" LOC = C15 | IOSTANDARD = LVCMOS33;
-NET "led(3)" LOC = B15 | IOSTANDARD = LVCMOS33;
-
-# ==== Prohibit Special Pins ====
-CONFIG PROHIBIT = T12;  # FPGA_INIT_B
-CONFIG PROHIBIT = D5;   # FPGA_PUDC
-CONFIG PROHIBIT = P4;   # PSOC_FPGA_M0
-CONFIG PROHIBIT = N4;   # PSOC_FPGA_M1
-CONFIG PROHIBIT = R2;   # PSOC_FPGA_M2
diff --git a/boards/avnet-sp3aevl/synthesis/load.cmd b/boards/avnet-sp3aevl/synthesis/load.cmd
deleted file mode 100644
index 52de4fc3..00000000
--- a/boards/avnet-sp3aevl/synthesis/load.cmd
+++ /dev/null
@@ -1,6 +0,0 @@
-setMode -bscan
-setCable -p auto
-identify
-assignfile -p 1 -file system.bit
-program -p 1
-quit
diff --git a/boards/avnet-sp3aevl/synthesis/system.xst b/boards/avnet-sp3aevl/synthesis/system.xst
deleted file mode 100644
index 19f8bea3..00000000
--- a/boards/avnet-sp3aevl/synthesis/system.xst
+++ /dev/null
@@ -1,9 +0,0 @@
-run
--ifn system.prj
--top system
--ifmt MIXED
--opt_mode AREA
--opt_level 2
--ofn system.ngc
--p xc3s400a-ft256-4
--register_balancing yes
diff --git a/boards/avnet-sp3aevl/synthesis/xst.ucf b/boards/avnet-sp3aevl/synthesis/xst.ucf
deleted file mode 100644
index e69de29b..00000000
diff --git a/boards/avnet-sp3aevl/test/Makefile b/boards/avnet-sp3aevl/test/Makefile
deleted file mode 100644
index 80d27427..00000000
--- a/boards/avnet-sp3aevl/test/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-TOPDIR?=$(shell pwd)
-BOARD_DIR=$(TOPDIR)/../rtl
-CORES_DIR=$(TOPDIR)/../../../cores
-
-include ../sources.mak
-
-SIM_SRC=$(TOPDIR)/system_tb.v $(CORES_DIR)/hpdmc_ddr32/test/iddr.v $(CORES_DIR)/hpdmc_ddr32/test/oddr.v $(CORES_DIR)/hpdmc_ddr32/test/idelay.v
-
-SRC=$(SIM_SRC) $(BOARD_SRC) $(CORES_SRC)
-
-all: isim
-
-cversim: $(SRC) bios.rom
-	cver +define+SIMULATION +incdir+$(BOARD_DIR) +incdir+$(CORES_DIR)/lm32/rtl $(SRC)
-
-isim: system bios.rom
-	./system
-
-system: $(SRC)
-	iverilog -D SIMULATION -I $(BOARD_DIR) -I $(CORES_DIR)/lm32/rtl -o system $(SRC)
-
-bios.rom: ../../../software/bios/bios.bin
-	../../../tools/bin2hex ../../../software/bios/bios.bin bios.rom 32768
-
-clean:
-	rm -f verilog.log bios.rom system
-
-.PHONY: clean cversim isim
diff --git a/boards/avnet-sp3aevl/test/system_tb.v b/boards/avnet-sp3aevl/test/system_tb.v
deleted file mode 100644
index d9e69297..00000000
--- a/boards/avnet-sp3aevl/test/system_tb.v
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Milkymist VJ SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-`timescale 1ns/1ps
-
-module system_tb();
-
-reg sys_clk;
-reg resetin;
-
-initial sys_clk = 1'b0;
-always #5 sys_clk = ~sys_clk;
-
-initial begin
-	resetin = 1'b1;
-	#200 resetin = 1'b0;
-end
-
-wire [21:0] flash_adr;
-reg [31:0] flash_d;
-reg [7:0] flash_d8;
-reg [31:0] flash[0:32767];
-initial $readmemh("bios.rom", flash);
-always @(flash_adr) begin
-	#110;
-	flash_d = flash[flash_adr[21:2]];
-	case(flash_adr[1:0])
-		2'b00: flash_d8 = flash_d[31:24];
-		2'b01: flash_d8 = flash_d[23:16];
-		2'b10: flash_d8 = flash_d[15:8];
-		2'b11: flash_d8 = flash_d[7:0];
-	endcase
-end
-
-system system(
-	.clkin(sys_clk),
-	.resetin(resetin),
-
-	.flash_adr(flash_adr),
-	.flash_d(flash_d8),
-
-	.uart_rxd(),
-	.uart_txd()
-);
-
-endmodule
diff --git a/clean_all.sh b/clean_all.sh
index 0b164384..36fe1865 100755
--- a/clean_all.sh
+++ b/clean_all.sh
@@ -13,7 +13,6 @@ cd $BASEDIR/software/bios && make clean
 cd $BASEDIR/software/demo && make clean
 
 cd $BASEDIR/boards/xilinx-ml401/synthesis && make -f common.mak clean
-cd $BASEDIR/boards/avnet-sp3aevl/synthesis && make -f common.mak clean
 cd $BASEDIR/boards/milkymist-one/synthesis && make -f common.mak clean
 
 cd $BASEDIR/doc && make clean
diff --git a/software/bios/main.c b/software/bios/main.c
index 13d3d20e..f39af840 100644
--- a/software/bios/main.c
+++ b/software/bios/main.c
@@ -38,18 +38,12 @@ const struct board_desc *brd_desc;
 
 /* SDRAM functions */
 
-static int sdram_enabled;
 static int dqs_ps;
 
 static void ddrinit()
 {
 	volatile unsigned int i;
 
-	if(!sdram_enabled) {
-		printf("E: Command disabled\n");
-		return;
-	}
-	
 	putsnonl("I: Initializing SDRAM [DDR200 CL=2 BL=8]...");
 	/* Bring CKE high */
 	CSR_HPDMC_SYSTEM = HPDMC_SYSTEM_BYPASS|HPDMC_SYSTEM_RESET|HPDMC_SYSTEM_CKE;
@@ -89,11 +83,6 @@ static int plltest()
 {
 	int ok1, ok2;
 
-	if(!sdram_enabled) {
-		printf("E: Command disabled\n");
-		return 0;
-	}
-
 	printf("I: Checking if SDRAM clocking is functional:\n");
 	ok1 = CSR_HPDMC_IODELAY & HPDMC_PLL1_LOCKED;
 	ok2 = CSR_HPDMC_IODELAY & HPDMC_PLL2_LOCKED;
@@ -109,11 +98,6 @@ static int memtest(unsigned int div)
 	unsigned int i;
 	unsigned int size;
 
-	if(!sdram_enabled) {
-		printf("E: Command disabled\n");
-		return 0;
-	}
-	
 	putsnonl("I: SDRAM test...");
 
 	size = brd_desc->sdram_size*1024*1024/(4*div);
@@ -147,11 +131,6 @@ static void calibrate()
 	int quit;
 	char c;
 
-	if(!sdram_enabled) {
-		printf("E: Command disabled\n");
-		return;
-	}
-	
 	printf("================================\n");
 	printf("DDR SDRAM calibration tool\n");
 	printf("================================\n");
@@ -548,7 +527,7 @@ static void display_board()
 
 static const char banner[] =
 	"\nMILKYMIST(tm) v"VERSION" BIOS\thttp://www.milkymist.org\n"
-	"(c) 2007, 2008, 2009 Sebastien Bourdeauducq\n\n"
+	"(c) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq\n\n"
 	"This program is free software: you can redistribute it and/or modify\n"
 	"it under the terms of the GNU General Public License as published by\n"
 	"the Free Software Foundation, version 3 of the License.\n\n";
@@ -585,24 +564,17 @@ int main(int i, char **c)
 	
 	crcbios();
 	display_board();
-
-	sdram_enabled = 1;
 	
-	if(brd_desc->sdram_size > 0) {
-		if(plltest()) {
-			ddrinit();
-			flush_bridge_cache();
-
-			if(memtest(8))
-				boot_sequence();
-			else
-				printf("E: Aborted boot on memory error\n");
-		} else
-			printf("E: Faulty SDRAM clocking\n");
-	} else {
-		printf("I: No SDRAM on this evaluation board, not booting\n");
-		sdram_enabled = 0;
-	}
+	if(plltest()) {
+		ddrinit();
+		flush_bridge_cache();
+
+		if(memtest(8))
+			boot_sequence();
+		else
+			printf("E: Aborted boot on memory error\n");
+	} else
+		printf("E: Faulty SDRAM clocking\n");
 
 	splash_showerr();
 	while(1) {
diff --git a/software/libbase/board.c b/software/libbase/board.c
index 0cce2804..55b33cc7 100644
--- a/software/libbase/board.c
+++ b/software/libbase/board.c
@@ -30,13 +30,6 @@ static const struct board_desc boards[3] = {
 		.ddr_dqsdelay = 244,
 		.memory_card = MEMCARD_SYSTEMACE
 	},
-	{
-		.id = 0x53334145, /* S3AE */
-		.name = "Avnet Spartan-3A evaluation kit",
-		.clk_frequency = 64000000,
-		.sdram_size = 0,
-		.memory_card = MEMCARD_NONE
-	},
 	{
 		.id = 0x4D4F4E45, /* MONE */
 		.name = "Milkymist One",