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softusb: added access to Navre's PC via CSR

This is for debugging. Removed reading back the reset status via CSR,
since it seems not very useful and we don't have to decode the address
this way.
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1 parent f1a0886 commit ff723302cd0725486fbd0624ed860f08d8856d93 @wpwrak wpwrak committed Mar 2, 2012
Showing with 20 additions and 7 deletions.
  1. +10 −3 cores/softusb/rtl/softusb.v
  2. +6 −3 cores/softusb/rtl/softusb_hostif.v
  3. +4 −1 cores/softusb/rtl/softusb_navre.v
@@ -76,8 +76,11 @@ softusb_timer timer(
.io_do(io_dr_timer)
);
+wire [pmem_width-1:0] dbg_pc;
+
softusb_hostif #(
- .csr_addr(csr_addr)
+ .csr_addr(csr_addr),
+ .pmem_width(pmem_width)
) hostif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
@@ -93,7 +96,9 @@ softusb_hostif #(
.irq(irq),
.io_we(io_we),
- .io_a(io_a)
+ .io_a(io_a),
+
+ .dbg_pc(dbg_pc)
);
softusb_sie sie(
@@ -178,7 +183,9 @@ softusb_navre #(
.io_we(io_we),
.io_a(io_a),
.io_do(io_dw),
- .io_di(io_dr_sie|io_dr_timer)
+ .io_di(io_dr_sie|io_dr_timer),
+
+ .dbg_pc(dbg_pc)
);
endmodule
@@ -16,7 +16,8 @@
*/
module softusb_hostif #(
- parameter csr_addr = 4'h0
+ parameter csr_addr = 4'h0,
+ parameter pmem_width = 12
) (
input sys_clk,
input sys_rst,
@@ -32,7 +33,9 @@ module softusb_hostif #(
output irq,
input io_we,
- input [5:0] io_a
+ input [5:0] io_a,
+
+ input [pmem_width-1:0] dbg_pc
);
wire csr_selected = csr_a[13:10] == csr_addr;
@@ -48,7 +51,7 @@ always @(posedge sys_clk) begin
if(csr_selected) begin
if(csr_we)
usb_rst0 <= csr_di[0];
- csr_do <= usb_rst0;
+ csr_do <= { dbg_pc, 1'b0 };
end
end
end
@@ -35,7 +35,9 @@ module softusb_navre #(
output reg io_we,
output [5:0] io_a,
output [7:0] io_do,
- input [7:0] io_di
+ input [7:0] io_di,
+
+ output reg [pmem_width-1:0] dbg_pc
);
/* Register file */
@@ -195,6 +197,7 @@ always @(posedge clk) begin
PC_SEL_Z: PC <= pZ - 1;
endcase
end
+ dbg_pc <= PC;
end
reg pmem_selz;
assign pmem_a = rst ?

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