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  • 11 commits
  • 9 files changed
  • 0 commit comments
  • 2 contributors
Commits on Nov 22, 2011
@mwalle mwalle sysctl: change offsets and new frequency register
Reorganize register offsets and introduce new register to read the system
clock frequency.
b960501
@mwalle mwalle sysctl: new debug control register
Introduce a debug control register. It can be used to lock the gdbstub ROM
and enable/disable bus errors. The gdbstub ROM will be read/writeable until
one writes the corresponding lock bit to this register. This will ease
future gdbstub updates.
c4acd1a
@mwalle mwalle monitor: introduce write lock
Make ROM writeable unless the lock is set.
514c022
@mwalle mwalle soc: connect write lock register to monitor core
d0a720b
@mwalle mwalle gdbstub: set correct uart speed
Set the UART speed to a fixed value when gdbstub is called and restore its
previous value if gdbstub exits.
58c4169
@mwalle mwalle update monitor rom
173f00d
@mwalle mwalle bios: lock gdbstub ROM
For now, unconditionally lock the GDB stub ROM as soon as possible.
631a826
@mwalle mwalle gdbstub: disable bus errors
Disable bus errors while the gdbstub is running. This will prevent nested
gdbstub invokations.
41cba8a
@mwalle mwalle soc: add enable signal to bus errors
327d65c
@mwalle mwalle bios: enable bus errors
By default bus errors are disabled, enable them.
efaf421
@sbourdeauducq sbourdeauducq sysctl: fix ICAP address decoding
0f65527
View
11 boards/milkymist-one/rtl/system.v
@@ -760,6 +760,7 @@ assign cpu_interrupt = {16'd0,
//---------------------------------------------------------------------------
// LM32 CPU
//---------------------------------------------------------------------------
+wire bus_errors_en;
wire cpuibus_err;
wire cpudbus_err;
`ifdef CFG_BUS_ERRORS_ENABLED
@@ -772,8 +773,8 @@ always @(posedge sys_clk) begin
locked_addr_i <= cpuibus_adr[31:18] == 14'd0;
locked_addr_d <= cpudbus_adr[31:18] == 14'd0;
end
-assign cpuibus_err = locked_addr_i & cpuibus_ack;
-assign cpudbus_err = locked_addr_d & cpudbus_ack;
+assign cpuibus_err = bus_errors_en & locked_addr_i & cpuibus_ack;
+assign cpudbus_err = bus_errors_en & locked_addr_d & cpudbus_ack;
`else
assign cpuibus_err = 1'b0;
assign cpudbus_err = 1'b0;
@@ -855,10 +856,12 @@ assign flash_ce_n = 1'b0;
//---------------------------------------------------------------------------
// Monitor ROM / RAM
//---------------------------------------------------------------------------
+wire debug_write_lock;
`ifdef CFG_ROM_DEBUG_ENABLED
monitor(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
+ .write_lock(debug_write_lock),
.wb_adr_i(monitor_adr),
.wb_dat_o(monitor_dat_r),
@@ -913,6 +916,7 @@ sysctl #(
.csr_addr(4'h1),
.ninputs(7),
.noutputs(2),
+ .clk_freq(`CLOCK_FREQUENCY),
.systemid(32'h11004D31) /* 1.1.0 final (0) on M1 */
) sysctl (
.sys_clk(sys_clk),
@@ -930,6 +934,9 @@ sysctl #(
.gpio_inputs({pcb_revision, btn3, btn2, btn1}),
.gpio_outputs({led2, led1}),
+ .debug_write_lock(debug_write_lock),
+ .bus_errors_en(bus_errors_en),
+
.capabilities(capabilities),
.hard_reset(hard_reset)
);
View
270 cores/monitor/rtl/gdbstub.rom
@@ -180,13 +180,13 @@ c3e00000
e3fffffd
c3a00000
78021000
-38420fb8
+38421030
28410000
28220000
20420002
4440fffe
78031000
-38630fb8
+38631030
28610000
34020002
58220000
@@ -197,7 +197,7 @@ c3a00000
7802e000
58410000
78021000
-38420fb8
+38421030
28410000
28220000
20420001
@@ -222,7 +222,7 @@ c3a00000
3441ffc9
c3a00000
78041000
-3884100c
+38841094
e000000d
40250000
3463ffff
@@ -313,7 +313,7 @@ c3a00000
b8205800
29620084
78011000
-38211004
+3821108c
20420007
b4220800
10230000
@@ -323,7 +323,7 @@ b4220800
14640004
30410000
78011000
-3821100c
+38211094
2063000f
2084000f
b4242000
@@ -374,7 +374,7 @@ c3a00000
780d1000
780b1000
39ad1804
-396b0fc4
+396b104c
3410002b
34010024
fbffff49
@@ -466,16 +466,16 @@ b4823800
e0000002
fbffff20
78011000
-38210fd8
+38211060
e0000003
78011000
-38210fdc
+38211064
fbffffc3
2b9d0004
2b8b0008
379c0014
c3a00000
-379cffb0
+379cffa8
5b8b0044
5b8c0040
5b8d003c
@@ -494,11 +494,11 @@ c3a00000
5b9b0008
5b9d0004
78021000
-38420fbc
+38421034
b8206800
28410000
78031000
-38630fc0
+38631038
58200000
28610000
28220000
@@ -506,23 +506,43 @@ b8206800
34020001
58220000
fbfffeb1
+78041000
+3884103c
+28810000
78081000
-39080fb8
+39081030
+283b0000
+58200000
29010000
28220000
20420001
4440fffe
78021000
-38420fb8
+38421030
28410000
-283b0000
+78031000
+38631040
+28210000
+78081000
+39081044
+5b810048
+28610000
+29020000
+28240000
+28430000
+5b84004c
+78041000
+38841048
+28820000
+8c621000
+58220000
78011000
38211800
10210000
44200004
b9a00800
-fbffff28
-fbffff61
+fbffff14
+fbffff4d
78101000
780c1000
78171000
@@ -537,20 +557,20 @@ fbffff61
398c1b28
3af71800
3ad61b2b
-39ef0fdc
-3ab50fe4
-3a730fd8
+39ef1064
+3ab5106c
+3a731060
396b1e50
39ce1e4c
3a521e64
32000000
34190024
34180023
-fbfffe91
+fbfffe7d
5c39ffff
34110000
34140000
-fbfffe8d
+fbfffe79
b8201000
4439fffc
44380008
@@ -558,35 +578,35 @@ b681a000
b5910800
30220000
36310001
-3403031f
+3408031f
229400ff
-4c71fff6
+4d11fff6
b5918800
32200000
5c58ffef
-fbfffe7f
+fbfffe6b
202100ff
-fbfffe95
+fbfffe81
3c210004
203100ff
-fbfffe7a
+fbfffe66
202100ff
-fbfffe90
+fbfffe7c
b6210800
202100ff
46810004
3401002d
-fbfffe82
+fbfffe6e
e3ffffe1
3401002b
-fbfffe7f
+fbfffe6b
11820002
3401003a
5c410005
11810000
-fbfffe7a
+fbfffe66
11810001
-fbfffe78
+fbfffe64
11830000
34010001
32e10000
@@ -633,7 +653,7 @@ e000000c
5c610149
e0000071
b9a00800
-fbfffeb8
+fbfffea4
e0000145
b9a00800
ba001000
@@ -646,68 +666,68 @@ b9a01000
e0000040
78011000
38211b29
-5b810050
-3782004c
-37810050
-fbfffe88
+5b810058
+37820054
+37810058
+fbfffe74
4c010121
-2b810050
+2b810058
10220000
34210001
-5b810050
+5b810058
3401002c
5c41011b
-37810050
-37820048
-fbfffe7e
+37810058
+37820050
+fbfffe6a
4c010117
-2b830048
+2b830050
34010190
54610114
-2b81004c
+2b810054
ba001000
-fbfffe43
+fbfffe2f
5c200124
78011000
-38210fe0
-e000014c
+38211068
+e0000156
34010000
e0000002
34010001
-fbffff02
+fbfffeee
e000011c
78011000
38211b29
-5b810050
-3782004c
-37810050
-fbfffe68
+5b810058
+37820054
+37810058
+fbfffe54
4c010101
-2b81004c
+2b810054
ba001000
34030004
3c210002
b5a10800
-fbfffe2d
+fbfffe19
e000010e
78011000
38211b29
-5b810050
-3782004c
-37810050
-fbfffe5a
+5b810058
+37820054
+37810058
+fbfffe46
4c0100f3
-2b810050
+2b810058
3402003d
10230000
34210001
-5b810050
+5b810058
5c6200ed
-2b82004c
+2b820054
34030004
3c420002
b5a21000
-fbfffe2d
+fbfffe19
e00000e3
d1000000
d2000000
@@ -720,18 +740,18 @@ d2600000
34010044
5c6100f3
78011000
-38210fd8
-fbfffec8
-fbfffe99
+38211060
+fbfffeb4
+fbfffe85
e00000ee
78011000
38211b29
-5b810050
-3782004c
-37810050
-fbfffe38
+5b810058
+37820054
+37810058
+fbfffe24
4c010003
-2b81004c
+2b810054
59a10080
78011000
38211b28
@@ -745,21 +765,21 @@ fbfffe38
d1010000
e00000da
11910002
-5b960050
+5b960058
3401002c
5e2100c0
-37810050
-3782004c
-fbfffe23
+37810058
+37820054
+fbfffe0f
4c0100bc
-2b820050
+2b820058
10410000
34420001
-5b820050
+5b820058
5c3100b7
-37810050
-37820048
-fbfffe1a
+37810058
+37820050
+fbfffe06
4c0100b3
11820001
34010032
@@ -777,7 +797,7 @@ e0000062
e0000063
11820000
3401005a
-2b83004c
+2b830054
5c410034
90c01000
14420012
@@ -875,7 +895,7 @@ e0000002
34020004
11840000
3401005a
-2b83004c
+2b830054
5c81001f
b8400800
90c03800
@@ -936,30 +956,30 @@ e0000009
3c840002
e3ffffeb
ba600800
-e0000042
+e000004c
baa00800
-e0000040
+e000004a
b9e00800
-e000003e
+e0000048
7802e000
34010001
-3842103c
+3842107c
58410000
e000000e
78021000
78031000
38421b29
-38630fe8
+38631070
40440000
40610000
5c810007
-78081000
-39081b31
-4448002d
+78041000
+38841b31
+44440037
34420001
34630001
e3fffff8
-fbfffdac
+fbfffd98
e3fffe5f
d0600000
34000000
@@ -972,13 +992,23 @@ d0800000
34000000
34000000
78031000
-38630fb8
+2b880048
+38631030
28610000
-78081000
-23620004
-39080fbc
+78041000
+21020004
+38841040
58220000
-29010000
+2b88004c
+28810000
+78021000
+3842103c
+58280000
+28410000
+78031000
+38631034
+583b0000
+28610000
34020001
58220000
2b9d0004
@@ -998,15 +1028,19 @@ d0800000
2b980010
2b99000c
2b9b0008
-379c0050
+379c0058
c3a00000
78011000
-38210ff4
-fbfffdaf
-e3ffffd4
+3821107c
+fbfffd91
+e3ffffca
e0000008
e0000010
-e0001030
+e0001050
+e0001054
+e0000004
+e0001074
+001c2000
30313233
34353637
38396162
@@ -1030,41 +1064,7 @@ e0001030
38396162
63646566
00000000
-1f483ad7
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
+960a7788
00000000
00000000
00000000
View
6 cores/monitor/rtl/monitor.v
@@ -20,6 +20,8 @@ module monitor(
input sys_clk,
input sys_rst,
+ input write_lock,
+
input [31:0] wb_adr_i,
output reg [31:0] wb_dat_o,
input [31:0] wb_dat_i,
@@ -42,11 +44,11 @@ initial $readmemh("monitor.rom", mem);
/* write protect */
`ifdef CFG_GDBSTUB_ENABLED
-assign ram_we = (wb_adr_i[12] == 1'b1);
+assign ram_we = (wb_adr_i[12] == 1'b1) | ~write_lock;
wire [10:0] adr;
assign adr = wb_adr_i[12:2];
`else
-assign ram_we = (wb_adr_i[10:9] == 2'b11);
+assign ram_we = (wb_adr_i[10:9] == 2'b11) | ~write_lock;
wire [9:0] adr;
assign adr = wb_adr_i[10:2];
`endif
View
1  cores/monitor/test/tb_monitor.v
@@ -17,6 +17,7 @@ reg dat;
monitor dut(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
+ .write_lock(1'b1),
.wb_stb_i(wb_stb_i),
.wb_cyc_i(wb_cyc_i),
.wb_ack_o(wb_ack_o),
View
7 cores/sysctl/doc/sysctl.tex
@@ -68,11 +68,14 @@ \subsection{Counter register, offset 0x18/0x28}
This register holds the current value of the timer counter. It can be read or written at any time.
Writing it does not clear the trigger bit (bit 0 of the timer control register). The trigger bit should always be manually reset.
+\section{System Frequency}
+The system controller provides a 32-bit value defined at synthesis time that returns the system frequency of the SoC. It is readable from register 0x74. It is defined using the \verb!clk_freq! Verilog parameter.
+
\section{Capabilities}
-The system controller provides a 32-bit value intended to be used as user-defined bit mask that defines the presence of certain peripherals or features in the bitstream. It is readable from register 0x38. It is defined using the \verb!capabilities! input.
+The system controller provides a 32-bit value intended to be used as user-defined bit mask that defines the presence of certain peripherals or features in the bitstream. It is readable from register 0x78. It is defined using the \verb!capabilities! input.
\section{System identification}
-The system controller provides a 32-bit value defined at synthesis time that can be used to identify bitstreams or boards. The value is set by the \verb!systemid! Verilog parameter and read using the register 0x3c.
+The system controller provides a 32-bit value defined at synthesis time that can be used to identify bitstreams or boards. The value is set by the \verb!systemid! Verilog parameter and read using the register 0x7c.
Writing any value to this register sends a hard system reset by asserting the \verb!hard_reset! output.
View
82 cores/sysctl/rtl/sysctl.v
@@ -19,6 +19,7 @@ module sysctl #(
parameter csr_addr = 4'h0,
parameter ninputs = 16,
parameter noutputs = 16,
+ parameter clk_freq = 32'h00000000,
parameter systemid = 32'habadface
) (
input sys_clk,
@@ -41,6 +42,8 @@ module sysctl #(
input [31:0] capabilities,
+ output reg debug_write_lock,
+ output reg bus_errors_en,
output reg hard_reset
);
@@ -109,7 +112,7 @@ reg [7:0] debug_scratchpad;
wire csr_selected = csr_a[13:10] == csr_addr;
-assign icap_we = csr_selected & csr_we & (csr_a[3:0] == 4'b1101);
+assign icap_we = csr_selected & csr_we & (csr_a[4:0] == 5'b10000);
always @(posedge sys_clk) begin
if(sys_rst) begin
@@ -133,6 +136,8 @@ always @(posedge sys_clk) begin
hard_reset <= 1'b0;
debug_scratchpad <= 8'd0;
+ debug_write_lock <= 1'b0;
+ bus_errors_en <= 1'b0;
end else begin
timer0_irq <= 1'b0;
timer1_irq <= 1'b0;
@@ -153,56 +158,73 @@ always @(posedge sys_clk) begin
if(csr_selected) begin
/* CSR Writes */
if(csr_we) begin
- case(csr_a[3:0])
+ case(csr_a[4:0])
/* GPIO registers */
- // 0000 is GPIO IN and is read-only
- 4'b0001: gpio_outputs <= csr_di[noutputs-1:0];
- 4'b0010: gpio_irqen <= csr_di[ninputs-1:0];
+ // 00000 is GPIO IN and is read-only
+ 5'b00001: gpio_outputs <= csr_di[noutputs-1:0];
+ 5'b00010: gpio_irqen <= csr_di[ninputs-1:0];
/* Timer 0 registers */
- 4'b0100: begin
+ 5'b00100: begin
en0 <= csr_di[0];
ar0 <= csr_di[1];
end
- 4'b0101: compare0 <= csr_di;
- 4'b0110: counter0 <= csr_di;
+ 5'b00101: compare0 <= csr_di;
+ 5'b00110: counter0 <= csr_di;
/* Timer 1 registers */
- 4'b1000: begin
+ 5'b01000: begin
en1 <= csr_di[0];
ar1 <= csr_di[1];
end
- 4'b1001: compare1 <= csr_di;
- 4'b1010: counter1 <= csr_di;
+ 5'b01001: compare1 <= csr_di;
+ 5'b01010: counter1 <= csr_di;
+
+ /* ICAP */
+ // 10000 is ICAP and is handled separately
+
+ /* Debug monitor (gdbstub) */
+ 5'b10100: debug_scratchpad <= csr_di[7:0];
+ 5'b10101: begin
+ if(csr_di[0])
+ debug_write_lock <= 1'b1;
+ bus_errors_en = csr_di[1];
+ end
- 4'b1100: debug_scratchpad <= csr_di[7:0];
- // 1101 is ICAP and is handled separately
- // 1110 is capabilities and is read-only
- 4'b1111: hard_reset <= 1'b1;
+ // 11101 is clk_freq and is read-only
+ // 11110 is capabilities and is read-only
+ 5'b11111: hard_reset <= 1'b1;
endcase
end
/* CSR Reads */
- case(csr_a[3:0])
+ case(csr_a[4:0])
/* GPIO registers */
- 4'b0000: csr_do <= gpio_in;
- 4'b0001: csr_do <= gpio_outputs;
- 4'b0010: csr_do <= gpio_irqen;
+ 5'b00000: csr_do <= gpio_in;
+ 5'b00001: csr_do <= gpio_outputs;
+ 5'b00010: csr_do <= gpio_irqen;
/* Timer 0 registers */
- 4'b0100: csr_do <= {ar0, en0};
- 4'b0101: csr_do <= compare0;
- 4'b0110: csr_do <= counter0;
+ 5'b00100: csr_do <= {ar0, en0};
+ 5'b00101: csr_do <= compare0;
+ 5'b00110: csr_do <= counter0;
/* Timer 1 registers */
- 4'b1000: csr_do <= {ar1, en1};
- 4'b1001: csr_do <= compare1;
- 4'b1010: csr_do <= counter1;
-
- 4'b1100: csr_do <= debug_scratchpad;
- 4'b1101: csr_do <= icap_ready;
- 4'b1110: csr_do <= capabilities;
- 4'b1111: csr_do <= systemid;
+ 5'b01000: csr_do <= {ar1, en1};
+ 5'b01001: csr_do <= compare1;
+ 5'b01010: csr_do <= counter1;
+
+ /* ICAP */
+ 5'b10000: csr_do <= icap_ready;
+
+ /* Debug monitor (gdbstub) */
+ 5'b10100: csr_do <= debug_scratchpad;
+ 5'b10101: csr_do <= {bus_errors_en, debug_write_lock};
+
+ /* Read only SoC properties */
+ 5'b11101: csr_do <= clk_freq;
+ 5'b11110: csr_do <= capabilities;
+ 5'b11111: csr_do <= systemid;
endcase
end
end
View
6 software/bios/main.c
@@ -613,6 +613,12 @@ int main(int i, char **c)
{
char buffer[64];
+ /* lock gdbstub ROM */
+ CSR_DBG_CTRL = DBG_CTRL_GDB_ROM_LOCK;
+
+ /* enable bus errors */
+ CSR_DBG_CTRL = DBG_CTRL_BUS_ERR_EN;
+
CSR_GPIO_OUT = GPIO_LED1;
rescue = !((unsigned int)main > FLASH_OFFSET_REGULAR_BIOS);
View
18 software/gdbstub/gdbstub.c
@@ -29,6 +29,8 @@
#define SUPPORT_Z_CMD 1
#define SUPPORT_Q_CMD 1
+#define GDBSTUB_UART_SPEED 115200
+
/* see crt0.S */
extern void clear_bss(void);
@@ -671,6 +673,8 @@ static void cmd_query(void)
void handle_exception(unsigned int *registers)
{
unsigned int stat;
+ unsigned int uart_div;
+ unsigned int dbg_ctrl;
/*
* make sure break is disabled.
@@ -688,12 +692,20 @@ void handle_exception(unsigned int *registers)
clear_bss();
}
+ /* disable bus errors */
+ dbg_ctrl = CSR_DBG_CTRL;
+ CSR_DBG_CTRL = 0;
+
/* wait until TX transaction is finished. If there was a transmission in
* progress, the event bit will be set. In this case, the gdbstub won't clear
* it after it is terminated. */
while(!(CSR_UART_STAT & UART_STAT_THRE));
stat = CSR_UART_STAT;
+ /* save UART divider and set own speed */
+ uart_div = CSR_UART_DIVISOR;
+ CSR_UART_DIVISOR = CSR_FREQUENCY / 16 / GDBSTUB_UART_SPEED;
+
/* reply to host that an exception has occured */
if (gdb_connected) {
cmd_status(registers);
@@ -770,6 +782,12 @@ void handle_exception(unsigned int *registers)
/* clear TX event if there was no transmission in progress */
CSR_UART_STAT = stat & UART_STAT_TX_EVT;
+ /* restore UART divider */
+ CSR_UART_DIVISOR = uart_div;
+
+ /* restore dbg control register */
+ CSR_DBG_CTRL = dbg_ctrl;
+
/* reenable break */
CSR_UART_DEBUG = UART_DEBUG_BREAK_EN;
}
View
14 software/include/hw/sysctl.h
@@ -35,15 +35,21 @@
#define TIMER_ENABLE (0x01)
#define TIMER_AUTORESTART (0x02)
-#define CSR_DBG_SCRATCHPAD MMPTR(0xe0001030)
-#define CSR_ICAP MMPTR(0xe0001034)
+#define CSR_ICAP MMPTR(0xe0001040)
#define ICAP_READY (0x01)
#define ICAP_CE (0x10000)
#define ICAP_WRITE (0x20000)
-#define CSR_CAPABILITIES MMPTR(0xe0001038)
-#define CSR_SYSTEM_ID MMPTR(0xe000103c)
+#define CSR_DBG_SCRATCHPAD MMPTR(0xe0001050)
+#define CSR_DBG_CTRL MMPTR(0xe0001054)
+
+#define DBG_CTRL_GDB_ROM_LOCK (0x01)
+#define DBG_CTRL_BUS_ERR_EN (0x02)
+
+#define CSR_FREQUENCY MMPTR(0xe0001074)
+#define CSR_CAPABILITIES MMPTR(0xe0001078)
+#define CSR_SYSTEM_ID MMPTR(0xe000107c)
#endif /* __HW_SYSCTL_H */

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