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  • 9 files changed
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Nov 22, 2011
Michael Walle sysctl: change offsets and new frequency register
Reorganize register offsets and introduce new register to read the system
clock frequency.
b960501
Michael Walle sysctl: new debug control register
Introduce a debug control register. It can be used to lock the gdbstub ROM
and enable/disable bus errors. The gdbstub ROM will be read/writeable until
one writes the corresponding lock bit to this register. This will ease
future gdbstub updates.
c4acd1a
Michael Walle monitor: introduce write lock
Make ROM writeable unless the lock is set.
514c022
Michael Walle soc: connect write lock register to monitor core d0a720b
Michael Walle gdbstub: set correct uart speed
Set the UART speed to a fixed value when gdbstub is called and restore its
previous value if gdbstub exits.
58c4169
Michael Walle update monitor rom 173f00d
Michael Walle bios: lock gdbstub ROM
For now, unconditionally lock the GDB stub ROM as soon as possible.
631a826
Michael Walle gdbstub: disable bus errors
Disable bus errors while the gdbstub is running. This will prevent nested
gdbstub invokations.
41cba8a
Michael Walle soc: add enable signal to bus errors 327d65c
Michael Walle bios: enable bus errors
By default bus errors are disabled, enable them.
efaf421
Sébastien Bourdeauducq sysctl: fix ICAP address decoding 0f65527
11  boards/milkymist-one/rtl/system.v
@@ -760,6 +760,7 @@ assign cpu_interrupt = {16'd0,
760 760
 //---------------------------------------------------------------------------
761 761
 // LM32 CPU
762 762
 //---------------------------------------------------------------------------
  763
+wire bus_errors_en;
763 764
 wire cpuibus_err;
764 765
 wire cpudbus_err;
765 766
 `ifdef CFG_BUS_ERRORS_ENABLED
@@ -772,8 +773,8 @@ always @(posedge sys_clk) begin
772 773
 	locked_addr_i <= cpuibus_adr[31:18] == 14'd0;
773 774
 	locked_addr_d <= cpudbus_adr[31:18] == 14'd0;
774 775
 end
775  
-assign cpuibus_err = locked_addr_i & cpuibus_ack;
776  
-assign cpudbus_err = locked_addr_d & cpudbus_ack;
  776
+assign cpuibus_err = bus_errors_en & locked_addr_i & cpuibus_ack;
  777
+assign cpudbus_err = bus_errors_en & locked_addr_d & cpudbus_ack;
777 778
 `else
778 779
 assign cpuibus_err = 1'b0;
779 780
 assign cpudbus_err = 1'b0;
@@ -855,10 +856,12 @@ assign flash_ce_n = 1'b0;
855 856
 //---------------------------------------------------------------------------
856 857
 // Monitor ROM / RAM
857 858
 //---------------------------------------------------------------------------
  859
+wire debug_write_lock;
858 860
 `ifdef CFG_ROM_DEBUG_ENABLED
859 861
 monitor(
860 862
 	.sys_clk(sys_clk),
861 863
 	.sys_rst(sys_rst),
  864
+	.write_lock(debug_write_lock),
862 865
 
863 866
 	.wb_adr_i(monitor_adr),
864 867
 	.wb_dat_o(monitor_dat_r),
@@ -913,6 +916,7 @@ sysctl #(
913 916
 	.csr_addr(4'h1),
914 917
 	.ninputs(7),
915 918
 	.noutputs(2),
  919
+	.clk_freq(`CLOCK_FREQUENCY),
916 920
 	.systemid(32'h11004D31) /* 1.1.0 final (0) on M1 */
917 921
 ) sysctl (
918 922
 	.sys_clk(sys_clk),
@@ -930,6 +934,9 @@ sysctl #(
930 934
 	.gpio_inputs({pcb_revision, btn3, btn2, btn1}),
931 935
 	.gpio_outputs({led2, led1}),
932 936
 
  937
+	.debug_write_lock(debug_write_lock),
  938
+	.bus_errors_en(bus_errors_en),
  939
+
933 940
 	.capabilities(capabilities),
934 941
 	.hard_reset(hard_reset)
935 942
 );
270  cores/monitor/rtl/gdbstub.rom
@@ -180,13 +180,13 @@ c3e00000
180 180
 e3fffffd
181 181
 c3a00000
182 182
 78021000
183  
-38420fb8
  183
+38421030
184 184
 28410000
185 185
 28220000
186 186
 20420002
187 187
 4440fffe
188 188
 78031000
189  
-38630fb8
  189
+38631030
190 190
 28610000
191 191
 34020002
192 192
 58220000
@@ -197,7 +197,7 @@ c3a00000
197 197
 7802e000
198 198
 58410000
199 199
 78021000
200  
-38420fb8
  200
+38421030
201 201
 28410000
202 202
 28220000
203 203
 20420001
@@ -222,7 +222,7 @@ c3a00000
222 222
 3441ffc9
223 223
 c3a00000
224 224
 78041000
225  
-3884100c
  225
+38841094
226 226
 e000000d
227 227
 40250000
228 228
 3463ffff
@@ -313,7 +313,7 @@ c3a00000
313 313
 b8205800
314 314
 29620084
315 315
 78011000
316  
-38211004
  316
+3821108c
317 317
 20420007
318 318
 b4220800
319 319
 10230000
@@ -323,7 +323,7 @@ b4220800
323 323
 14640004
324 324
 30410000
325 325
 78011000
326  
-3821100c
  326
+38211094
327 327
 2063000f
328 328
 2084000f
329 329
 b4242000
@@ -374,7 +374,7 @@ c3a00000
374 374
 780d1000
375 375
 780b1000
376 376
 39ad1804
377  
-396b0fc4
  377
+396b104c
378 378
 3410002b
379 379
 34010024
380 380
 fbffff49
@@ -466,16 +466,16 @@ b4823800
466 466
 e0000002
467 467
 fbffff20
468 468
 78011000
469  
-38210fd8
  469
+38211060
470 470
 e0000003
471 471
 78011000
472  
-38210fdc
  472
+38211064
473 473
 fbffffc3
474 474
 2b9d0004
475 475
 2b8b0008
476 476
 379c0014
477 477
 c3a00000
478  
-379cffb0
  478
+379cffa8
479 479
 5b8b0044
480 480
 5b8c0040
481 481
 5b8d003c
@@ -494,11 +494,11 @@ c3a00000
494 494
 5b9b0008
495 495
 5b9d0004
496 496
 78021000
497  
-38420fbc
  497
+38421034
498 498
 b8206800
499 499
 28410000
500 500
 78031000
501  
-38630fc0
  501
+38631038
502 502
 58200000
503 503
 28610000
504 504
 28220000
@@ -506,23 +506,43 @@ b8206800
506 506
 34020001
507 507
 58220000
508 508
 fbfffeb1
  509
+78041000
  510
+3884103c
  511
+28810000
509 512
 78081000
510  
-39080fb8
  513
+39081030
  514
+283b0000
  515
+58200000
511 516
 29010000
512 517
 28220000
513 518
 20420001
514 519
 4440fffe
515 520
 78021000
516  
-38420fb8
  521
+38421030
517 522
 28410000
518  
-283b0000
  523
+78031000
  524
+38631040
  525
+28210000
  526
+78081000
  527
+39081044
  528
+5b810048
  529
+28610000
  530
+29020000
  531
+28240000
  532
+28430000
  533
+5b84004c
  534
+78041000
  535
+38841048
  536
+28820000
  537
+8c621000
  538
+58220000
519 539
 78011000
520 540
 38211800
521 541
 10210000
522 542
 44200004
523 543
 b9a00800
524  
-fbffff28
525  
-fbffff61
  544
+fbffff14
  545
+fbffff4d
526 546
 78101000
527 547
 780c1000
528 548
 78171000
@@ -537,20 +557,20 @@ fbffff61
537 557
 398c1b28
538 558
 3af71800
539 559
 3ad61b2b
540  
-39ef0fdc
541  
-3ab50fe4
542  
-3a730fd8
  560
+39ef1064
  561
+3ab5106c
  562
+3a731060
543 563
 396b1e50
544 564
 39ce1e4c
545 565
 3a521e64
546 566
 32000000
547 567
 34190024
548 568
 34180023
549  
-fbfffe91
  569
+fbfffe7d
550 570
 5c39ffff
551 571
 34110000
552 572
 34140000
553  
-fbfffe8d
  573
+fbfffe79
554 574
 b8201000
555 575
 4439fffc
556 576
 44380008
@@ -558,35 +578,35 @@ b681a000
558 578
 b5910800
559 579
 30220000
560 580
 36310001
561  
-3403031f
  581
+3408031f
562 582
 229400ff
563  
-4c71fff6
  583
+4d11fff6
564 584
 b5918800
565 585
 32200000
566 586
 5c58ffef
567  
-fbfffe7f
  587
+fbfffe6b
568 588
 202100ff
569  
-fbfffe95
  589
+fbfffe81
570 590
 3c210004
571 591
 203100ff
572  
-fbfffe7a
  592
+fbfffe66
573 593
 202100ff
574  
-fbfffe90
  594
+fbfffe7c
575 595
 b6210800
576 596
 202100ff
577 597
 46810004
578 598
 3401002d
579  
-fbfffe82
  599
+fbfffe6e
580 600
 e3ffffe1
581 601
 3401002b
582  
-fbfffe7f
  602
+fbfffe6b
583 603
 11820002
584 604
 3401003a
585 605
 5c410005
586 606
 11810000
587  
-fbfffe7a
  607
+fbfffe66
588 608
 11810001
589  
-fbfffe78
  609
+fbfffe64
590 610
 11830000
591 611
 34010001
592 612
 32e10000
@@ -633,7 +653,7 @@ e000000c
633 653
 5c610149
634 654
 e0000071
635 655
 b9a00800
636  
-fbfffeb8
  656
+fbfffea4
637 657
 e0000145
638 658
 b9a00800
639 659
 ba001000
@@ -646,68 +666,68 @@ b9a01000
646 666
 e0000040
647 667
 78011000
648 668
 38211b29
649  
-5b810050
650  
-3782004c
651  
-37810050
652  
-fbfffe88
  669
+5b810058
  670
+37820054
  671
+37810058
  672
+fbfffe74
653 673
 4c010121
654  
-2b810050
  674
+2b810058
655 675
 10220000
656 676
 34210001
657  
-5b810050
  677
+5b810058
658 678
 3401002c
659 679
 5c41011b
660  
-37810050
661  
-37820048
662  
-fbfffe7e
  680
+37810058
  681
+37820050
  682
+fbfffe6a
663 683
 4c010117
664  
-2b830048
  684
+2b830050
665 685
 34010190
666 686
 54610114
667  
-2b81004c
  687
+2b810054
668 688
 ba001000
669  
-fbfffe43
  689
+fbfffe2f
670 690
 5c200124
671 691
 78011000
672  
-38210fe0
673  
-e000014c
  692
+38211068
  693
+e0000156
674 694
 34010000
675 695
 e0000002
676 696
 34010001
677  
-fbffff02
  697
+fbfffeee
678 698
 e000011c
679 699
 78011000
680 700
 38211b29
681  
-5b810050
682  
-3782004c
683  
-37810050
684  
-fbfffe68
  701
+5b810058
  702
+37820054
  703
+37810058
  704
+fbfffe54
685 705
 4c010101
686  
-2b81004c
  706
+2b810054
687 707
 ba001000
688 708
 34030004
689 709
 3c210002
690 710
 b5a10800
691  
-fbfffe2d
  711
+fbfffe19
692 712
 e000010e
693 713
 78011000
694 714
 38211b29
695  
-5b810050
696  
-3782004c
697  
-37810050
698  
-fbfffe5a
  715
+5b810058
  716
+37820054
  717
+37810058
  718
+fbfffe46
699 719
 4c0100f3
700  
-2b810050
  720
+2b810058
701 721
 3402003d
702 722
 10230000
703 723
 34210001
704  
-5b810050
  724
+5b810058
705 725
 5c6200ed
706  
-2b82004c
  726
+2b820054
707 727
 34030004
708 728
 3c420002
709 729
 b5a21000
710  
-fbfffe2d
  730
+fbfffe19
711 731
 e00000e3
712 732
 d1000000
713 733
 d2000000
@@ -720,18 +740,18 @@ d2600000
720 740
 34010044
721 741
 5c6100f3
722 742
 78011000
723  
-38210fd8
724  
-fbfffec8
725  
-fbfffe99
  743
+38211060
  744
+fbfffeb4
  745
+fbfffe85
726 746
 e00000ee
727 747
 78011000
728 748
 38211b29
729  
-5b810050
730  
-3782004c
731  
-37810050
732  
-fbfffe38
  749
+5b810058
  750
+37820054
  751
+37810058
  752
+fbfffe24
733 753
 4c010003
734  
-2b81004c
  754
+2b810054
735 755
 59a10080
736 756
 78011000
737 757
 38211b28
@@ -745,21 +765,21 @@ fbfffe38
745 765
 d1010000
746 766
 e00000da
747 767
 11910002
748  
-5b960050
  768
+5b960058
749 769
 3401002c
750 770
 5e2100c0
751  
-37810050
752  
-3782004c
753  
-fbfffe23
  771
+37810058
  772
+37820054
  773
+fbfffe0f
754 774
 4c0100bc
755  
-2b820050
  775
+2b820058
756 776
 10410000
757 777
 34420001
758  
-5b820050
  778
+5b820058
759 779
 5c3100b7
760  
-37810050
761  
-37820048
762  
-fbfffe1a
  780
+37810058
  781
+37820050
  782
+fbfffe06
763 783
 4c0100b3
764 784
 11820001
765 785
 34010032
@@ -777,7 +797,7 @@ e0000062
777 797
 e0000063
778 798
 11820000
779 799
 3401005a
780  
-2b83004c
  800
+2b830054
781 801
 5c410034
782 802
 90c01000
783 803
 14420012
@@ -875,7 +895,7 @@ e0000002
875 895
 34020004
876 896
 11840000
877 897
 3401005a
878  
-2b83004c
  898
+2b830054
879 899
 5c81001f
880 900
 b8400800
881 901
 90c03800
@@ -936,30 +956,30 @@ e0000009
936 956
 3c840002
937 957
 e3ffffeb
938 958
 ba600800
939  
-e0000042
  959
+e000004c
940 960
 baa00800
941  
-e0000040
  961
+e000004a
942 962
 b9e00800
943  
-e000003e
  963
+e0000048
944 964
 7802e000
945 965
 34010001
946  
-3842103c
  966
+3842107c
947 967
 58410000
948 968
 e000000e
949 969
 78021000
950 970
 78031000
951 971
 38421b29
952  
-38630fe8
  972
+38631070
953 973
 40440000
954 974
 40610000
955 975
 5c810007
956  
-78081000
957  
-39081b31
958  
-4448002d
  976
+78041000
  977
+38841b31
  978
+44440037
959 979
 34420001
960 980
 34630001
961 981
 e3fffff8
962  
-fbfffdac
  982
+fbfffd98
963 983
 e3fffe5f
964 984
 d0600000
965 985
 34000000
@@ -972,13 +992,23 @@ d0800000
972 992
 34000000
973 993
 34000000
974 994
 78031000
975  
-38630fb8
  995
+2b880048
  996
+38631030
976 997
 28610000
977  
-78081000
978  
-23620004
979  
-39080fbc
  998
+78041000
  999
+21020004
  1000
+38841040
980 1001
 58220000
981  
-29010000
  1002
+2b88004c
  1003
+28810000
  1004
+78021000
  1005
+3842103c
  1006
+58280000
  1007
+28410000
  1008
+78031000
  1009
+38631034
  1010
+583b0000
  1011
+28610000
982 1012
 34020001
983 1013
 58220000
984 1014
 2b9d0004
@@ -998,15 +1028,19 @@ d0800000
998 1028
 2b980010
999 1029
 2b99000c
1000 1030
 2b9b0008
1001  
-379c0050
  1031
+379c0058
1002 1032
 c3a00000
1003 1033
 78011000
1004  
-38210ff4
1005  
-fbfffdaf
1006  
-e3ffffd4
  1034
+3821107c
  1035
+fbfffd91
  1036
+e3ffffca
1007 1037
 e0000008
1008 1038
 e0000010
1009  
-e0001030
  1039
+e0001050
  1040
+e0001054
  1041
+e0000004
  1042
+e0001074
  1043
+001c2000
1010 1044
 30313233
1011 1045
 34353637
1012 1046
 38396162
@@ -1030,41 +1064,7 @@ e0001030
1030 1064
 38396162
1031 1065
 63646566
1032 1066
 00000000
1033  
-1f483ad7
1034  
-00000000
1035  
-00000000
1036  
-00000000
1037  
-00000000
1038  
-00000000
1039  
-00000000
1040  
-00000000
1041  
-00000000
1042  
-00000000
1043  
-00000000
1044  
-00000000
1045  
-00000000
1046  
-00000000
1047  
-00000000
1048  
-00000000
1049  
-00000000
1050  
-00000000
1051  
-00000000
1052  
-00000000
1053  
-00000000
1054  
-00000000
1055  
-00000000
1056  
-00000000
1057  
-00000000
1058  
-00000000
1059  
-00000000
1060  
-00000000
1061  
-00000000
1062  
-00000000
1063  
-00000000
1064  
-00000000
1065  
-00000000
1066  
-00000000
1067  
-00000000
  1067
+960a7788
1068 1068
 00000000
1069 1069
 00000000
1070 1070
 00000000
6  cores/monitor/rtl/monitor.v
@@ -20,6 +20,8 @@ module monitor(
20 20
 	input sys_clk,
21 21
 	input sys_rst,
22 22
 
  23
+	input write_lock,
  24
+
23 25
 	input [31:0] wb_adr_i,
24 26
 	output reg [31:0] wb_dat_o,
25 27
 	input [31:0] wb_dat_i,
@@ -42,11 +44,11 @@ initial $readmemh("monitor.rom", mem);
42 44
 
43 45
 /* write protect */
44 46
 `ifdef CFG_GDBSTUB_ENABLED
45  
-assign ram_we = (wb_adr_i[12] == 1'b1);
  47
+assign ram_we = (wb_adr_i[12] == 1'b1) | ~write_lock;
46 48
 wire [10:0] adr;
47 49
 assign adr = wb_adr_i[12:2];
48 50
 `else
49  
-assign ram_we = (wb_adr_i[10:9] == 2'b11);
  51
+assign ram_we = (wb_adr_i[10:9] == 2'b11) | ~write_lock;
50 52
 wire [9:0] adr;
51 53
 assign adr = wb_adr_i[10:2];
52 54
 `endif
1  cores/monitor/test/tb_monitor.v
@@ -17,6 +17,7 @@ reg dat;
17 17
 monitor dut(
18 18
 	.sys_clk(sys_clk),
19 19
 	.sys_rst(sys_rst),
  20
+	.write_lock(1'b1),
20 21
 	.wb_stb_i(wb_stb_i),
21 22
 	.wb_cyc_i(wb_cyc_i),
22 23
 	.wb_ack_o(wb_ack_o),
7  cores/sysctl/doc/sysctl.tex
@@ -68,11 +68,14 @@ \subsection{Counter register, offset 0x18/0x28}
68 68
 This register holds the current value of the timer counter. It can be read or written at any time.
69 69
 Writing it does not clear the trigger bit (bit 0 of the timer control register). The trigger bit should always be manually reset.
70 70
 
  71
+\section{System Frequency}
  72
+The system controller provides a 32-bit value defined at synthesis time that returns the system frequency of the SoC. It is readable from register 0x74. It is defined using the \verb!clk_freq! Verilog parameter.
  73
+
71 74
 \section{Capabilities}
72  
-The system controller provides a 32-bit value intended to be used as user-defined bit mask that defines the presence of certain peripherals or features in the bitstream. It is readable from register 0x38. It is defined  using the \verb!capabilities! input.
  75
+The system controller provides a 32-bit value intended to be used as user-defined bit mask that defines the presence of certain peripherals or features in the bitstream. It is readable from register 0x78. It is defined  using the \verb!capabilities! input.
73 76
 
74 77
 \section{System identification}
75  
-The system controller provides a 32-bit value defined at synthesis time that can be used to identify bitstreams or boards. The value is set by the \verb!systemid! Verilog parameter and read using the register 0x3c.
  78
+The system controller provides a 32-bit value defined at synthesis time that can be used to identify bitstreams or boards. The value is set by the \verb!systemid! Verilog parameter and read using the register 0x7c.
76 79
 
77 80
 Writing any value to this register sends a hard system reset by asserting the \verb!hard_reset! output.
78 81
 
82  cores/sysctl/rtl/sysctl.v
@@ -19,6 +19,7 @@ module sysctl #(
19 19
 	parameter csr_addr = 4'h0,
20 20
 	parameter ninputs = 16,
21 21
 	parameter noutputs = 16,
  22
+	parameter clk_freq = 32'h00000000,
22 23
 	parameter systemid = 32'habadface
23 24
 ) (
24 25
 	input sys_clk,
@@ -41,6 +42,8 @@ module sysctl #(
41 42
 
42 43
 	input [31:0] capabilities,
43 44
 
  45
+	output reg debug_write_lock,
  46
+	output reg bus_errors_en,
44 47
 	output reg hard_reset
45 48
 );
46 49
 
@@ -109,7 +112,7 @@ reg [7:0] debug_scratchpad;
109 112
 
110 113
 wire csr_selected = csr_a[13:10] == csr_addr;
111 114
 
112  
-assign icap_we = csr_selected & csr_we & (csr_a[3:0] == 4'b1101);
  115
+assign icap_we = csr_selected & csr_we & (csr_a[4:0] == 5'b10000);
113 116
 
114 117
 always @(posedge sys_clk) begin
115 118
 	if(sys_rst) begin
@@ -133,6 +136,8 @@ always @(posedge sys_clk) begin
133 136
 		hard_reset <= 1'b0;
134 137
 
135 138
 		debug_scratchpad <= 8'd0;
  139
+		debug_write_lock <= 1'b0;
  140
+		bus_errors_en <= 1'b0;
136 141
 	end else begin
137 142
 		timer0_irq <= 1'b0;
138 143
 		timer1_irq <= 1'b0;
@@ -153,56 +158,73 @@ always @(posedge sys_clk) begin
153 158
 		if(csr_selected) begin
154 159
 			/* CSR Writes */
155 160
 			if(csr_we) begin
156  
-				case(csr_a[3:0])
  161
+				case(csr_a[4:0])
157 162
 					/* GPIO registers */
158  
-					// 0000 is GPIO IN and is read-only
159  
-					4'b0001: gpio_outputs <= csr_di[noutputs-1:0];
160  
-					4'b0010: gpio_irqen <= csr_di[ninputs-1:0];
  163
+					// 00000 is GPIO IN and is read-only
  164
+					5'b00001: gpio_outputs <= csr_di[noutputs-1:0];
  165
+					5'b00010: gpio_irqen <= csr_di[ninputs-1:0];
161 166
 					
162 167
 					/* Timer 0 registers */
163  
-					4'b0100: begin
  168
+					5'b00100: begin
164 169
 						en0 <= csr_di[0];
165 170
 						ar0 <= csr_di[1];
166 171
 					end
167  
-					4'b0101: compare0 <= csr_di;
168  
-					4'b0110: counter0 <= csr_di;
  172
+					5'b00101: compare0 <= csr_di;
  173
+					5'b00110: counter0 <= csr_di;
169 174
 					
170 175
 					/* Timer 1 registers */
171  
-					4'b1000: begin
  176
+					5'b01000: begin
172 177
 						en1 <= csr_di[0];
173 178
 						ar1 <= csr_di[1];
174 179
 					end
175  
-					4'b1001: compare1 <= csr_di;
176  
-					4'b1010: counter1 <= csr_di;
  180
+					5'b01001: compare1 <= csr_di;
  181
+					5'b01010: counter1 <= csr_di;
  182
+
  183
+					/* ICAP */
  184
+					// 10000 is ICAP and is handled separately
  185
+
  186
+					/* Debug monitor (gdbstub) */
  187
+					5'b10100: debug_scratchpad <= csr_di[7:0];
  188
+					5'b10101: begin
  189
+						if(csr_di[0])
  190
+							debug_write_lock <= 1'b1;
  191
+						bus_errors_en = csr_di[1];
  192
+					end
177 193
 
178  
-					4'b1100: debug_scratchpad <= csr_di[7:0];
179  
-					// 1101 is ICAP and is handled separately
180  
-					// 1110 is capabilities and is read-only
181  
-					4'b1111: hard_reset <= 1'b1;
  194
+					// 11101 is clk_freq and is read-only
  195
+					// 11110 is capabilities and is read-only
  196
+					5'b11111: hard_reset <= 1'b1;
182 197
 				endcase
183 198
 			end
184 199
 		
185 200
 			/* CSR Reads */
186  
-			case(csr_a[3:0])
  201
+			case(csr_a[4:0])
187 202
 				/* GPIO registers */
188  
-				4'b0000: csr_do <= gpio_in;
189  
-				4'b0001: csr_do <= gpio_outputs;
190  
-				4'b0010: csr_do <= gpio_irqen;
  203
+				5'b00000: csr_do <= gpio_in;
  204
+				5'b00001: csr_do <= gpio_outputs;
  205
+				5'b00010: csr_do <= gpio_irqen;
191 206
 				
192 207
 				/* Timer 0 registers */
193  
-				4'b0100: csr_do <= {ar0, en0};
194  
-				4'b0101: csr_do <= compare0;
195  
-				4'b0110: csr_do <= counter0;
  208
+				5'b00100: csr_do <= {ar0, en0};
  209
+				5'b00101: csr_do <= compare0;
  210
+				5'b00110: csr_do <= counter0;
196 211
 				
197 212
 				/* Timer 1 registers */
198  
-				4'b1000: csr_do <= {ar1, en1};
199  
-				4'b1001: csr_do <= compare1;
200  
-				4'b1010: csr_do <= counter1;
201  
-
202  
-				4'b1100: csr_do <= debug_scratchpad;
203  
-				4'b1101: csr_do <= icap_ready;
204  
-				4'b1110: csr_do <= capabilities;
205  
-				4'b1111: csr_do <= systemid;
  213
+				5'b01000: csr_do <= {ar1, en1};
  214
+				5'b01001: csr_do <= compare1;
  215
+				5'b01010: csr_do <= counter1;
  216
+
  217
+				/* ICAP */
  218
+				5'b10000: csr_do <= icap_ready;
  219
+
  220
+				/* Debug monitor (gdbstub) */
  221
+				5'b10100: csr_do <= debug_scratchpad;
  222
+				5'b10101: csr_do <= {bus_errors_en, debug_write_lock};
  223
+
  224
+				/* Read only SoC properties */
  225
+				5'b11101: csr_do <= clk_freq;
  226
+				5'b11110: csr_do <= capabilities;
  227
+				5'b11111: csr_do <= systemid;
206 228
 			endcase
207 229
 		end
208 230
 	end
6  software/bios/main.c
@@ -613,6 +613,12 @@ int main(int i, char **c)
613 613
 {
614 614
 	char buffer[64];
615 615
 
  616
+	/* lock gdbstub ROM */
  617
+	CSR_DBG_CTRL = DBG_CTRL_GDB_ROM_LOCK;
  618
+
  619
+	/* enable bus errors */
  620
+	CSR_DBG_CTRL = DBG_CTRL_BUS_ERR_EN;
  621
+
616 622
 	CSR_GPIO_OUT = GPIO_LED1;
617 623
 	rescue = !((unsigned int)main > FLASH_OFFSET_REGULAR_BIOS);
618 624
 
18  software/gdbstub/gdbstub.c
@@ -29,6 +29,8 @@
29 29
 #define SUPPORT_Z_CMD 1
30 30
 #define SUPPORT_Q_CMD 1
31 31
 
  32
+#define GDBSTUB_UART_SPEED 115200
  33
+
32 34
 /* see crt0.S */
33 35
 extern void clear_bss(void);
34 36
 
@@ -671,6 +673,8 @@ static void cmd_query(void)
671 673
 void handle_exception(unsigned int *registers)
672 674
 {
673 675
     unsigned int stat;
  676
+    unsigned int uart_div;
  677
+    unsigned int dbg_ctrl;
674 678
 
675 679
     /*
676 680
      * make sure break is disabled.
@@ -688,12 +692,20 @@ void handle_exception(unsigned int *registers)
688 692
         clear_bss();
689 693
     }
690 694
 
  695
+    /* disable bus errors */
  696
+    dbg_ctrl = CSR_DBG_CTRL;
  697
+    CSR_DBG_CTRL = 0;
  698
+
691 699
     /* wait until TX transaction is finished. If there was a transmission in
692 700
      * progress, the event bit will be set. In this case, the gdbstub won't clear
693 701
      * it after it is terminated. */
694 702
     while(!(CSR_UART_STAT & UART_STAT_THRE));
695 703
     stat = CSR_UART_STAT;
696 704
 
  705
+    /* save UART divider and set own speed */
  706
+    uart_div = CSR_UART_DIVISOR;
  707
+    CSR_UART_DIVISOR = CSR_FREQUENCY / 16 / GDBSTUB_UART_SPEED;
  708
+
697 709
     /* reply to host that an exception has occured */
698 710
     if (gdb_connected) {
699 711
         cmd_status(registers);
@@ -770,6 +782,12 @@ void handle_exception(unsigned int *registers)
770 782
     /* clear TX event if there was no transmission in progress */
771 783
     CSR_UART_STAT = stat & UART_STAT_TX_EVT;
772 784
 
  785
+    /* restore UART divider */
  786
+    CSR_UART_DIVISOR = uart_div;
  787
+
  788
+    /* restore dbg control register */
  789
+    CSR_DBG_CTRL = dbg_ctrl;
  790
+
773 791
     /* reenable break */
774 792
     CSR_UART_DEBUG = UART_DEBUG_BREAK_EN;
775 793
 }
14  software/include/hw/sysctl.h
@@ -35,15 +35,21 @@
35 35
 #define TIMER_ENABLE		(0x01)
36 36
 #define TIMER_AUTORESTART	(0x02)
37 37
 
38  
-#define CSR_DBG_SCRATCHPAD	MMPTR(0xe0001030)
39  
-#define CSR_ICAP		MMPTR(0xe0001034)
  38
+#define CSR_ICAP		MMPTR(0xe0001040)
40 39
 
41 40
 #define ICAP_READY		(0x01)
42 41
 
43 42
 #define ICAP_CE			(0x10000)
44 43
 #define ICAP_WRITE		(0x20000)
45 44
 
46  
-#define CSR_CAPABILITIES	MMPTR(0xe0001038)
47  
-#define CSR_SYSTEM_ID		MMPTR(0xe000103c)
  45
+#define CSR_DBG_SCRATCHPAD	MMPTR(0xe0001050)
  46
+#define CSR_DBG_CTRL		MMPTR(0xe0001054)
  47
+
  48
+#define DBG_CTRL_GDB_ROM_LOCK	(0x01)
  49
+#define DBG_CTRL_BUS_ERR_EN	(0x02)
  50
+
  51
+#define CSR_FREQUENCY		MMPTR(0xe0001074)
  52
+#define CSR_CAPABILITIES	MMPTR(0xe0001078)
  53
+#define CSR_SYSTEM_ID		MMPTR(0xe000107c)
48 54
 
49 55
 #endif /* __HW_SYSCTL_H */

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