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23  boards/milkymist-one/rtl/system.v
@@ -720,8 +720,7 @@ fmlbrg #(
720 720
 //---------------------------------------------------------------------------
721 721
 // Interrupts
722 722
 //---------------------------------------------------------------------------
723  
-wire uartrx_irq;
724  
-wire uarttx_irq;
  723
+wire uart_irq;
725 724
 wire gpio_irq;
726 725
 wire timer0_irq;
727 726
 wire timer1_irq;
@@ -734,17 +733,15 @@ wire tmu_irq;
734 733
 wire ethernetrx_irq;
735 734
 wire ethernettx_irq;
736 735
 wire videoin_irq;
737  
-wire midirx_irq;
738  
-wire miditx_irq;
  736
+wire midi_irq;
739 737
 wire ir_irq;
740 738
 wire usb_irq;
741 739
 
742 740
 wire [31:0] cpu_interrupt;
743  
-assign cpu_interrupt = {14'd0,
  741
+assign cpu_interrupt = {16'd0,
744 742
 	usb_irq,
745 743
 	ir_irq,
746  
-	miditx_irq,
747  
-	midirx_irq,
  744
+	midi_irq,
748 745
 	videoin_irq,
749 746
 	ethernettx_irq,
750 747
 	ethernetrx_irq,
@@ -757,8 +754,7 @@ assign cpu_interrupt = {14'd0,
757 754
 	timer1_irq,
758 755
 	timer0_irq,
759 756
 	gpio_irq,
760  
-	uarttx_irq,
761  
-	uartrx_irq
  757
+	uart_irq
762 758
 };
763 759
 
764 760
 //---------------------------------------------------------------------------
@@ -876,8 +872,7 @@ uart #(
876 872
 	.csr_di(csr_dw),
877 873
 	.csr_do(csr_dr_uart),
878 874
 
879  
-	.rx_irq(uartrx_irq),
880  
-	.tx_irq(uarttx_irq),
  875
+	.irq(uart_irq),
881 876
 
882 877
 	.uart_rx(uart_rx),
883 878
 	.uart_tx(uart_tx),
@@ -1383,16 +1378,14 @@ uart #(
1383 1378
 	.csr_di(csr_dw),
1384 1379
 	.csr_do(csr_dr_midi),
1385 1380
 
1386  
-	.rx_irq(midirx_irq),
1387  
-	.tx_irq(miditx_irq),
  1381
+	.irq(midi_irq),
1388 1382
 
1389 1383
 	.uart_rx(midi_rx),
1390 1384
 	.uart_tx(midi_tx)
1391 1385
 );
1392 1386
 `else
1393 1387
 assign csr_dr_midi = 32'd0;
1394  
-assign midirx_irq = 1'b0;
1395  
-assign miditx_irq = 1'b0;
  1388
+assign midi_irq = 1'b0;
1396 1389
 assign midi_tx = 1'b1;
1397 1390
 `endif
1398 1391
 
182  cores/monitor/rtl/gdbstub.rom
@@ -12,7 +12,7 @@ e0000005
12 12
 581d0000
13 13
 f8000034
14 14
 5b9f0080
15  
-f80001c9
  15
+f80001cf
16 16
 e000008f
17 17
 98000000
18 18
 78001000
@@ -20,7 +20,7 @@ e000008f
20 20
 581d0000
21 21
 f800002c
22 22
 5b9e0080
23  
-f80001c1
  23
+f80001c7
24 24
 e0000079
25 25
 98000000
26 26
 78001000
@@ -28,7 +28,7 @@ e0000079
28 28
 581d0000
29 29
 f8000024
30 30
 5b9f0080
31  
-f80001b9
  31
+f80001bf
32 32
 e000007f
33 33
 98000000
34 34
 78001000
@@ -36,7 +36,7 @@ e000007f
36 36
 581d0000
37 37
 f800001c
38 38
 5b9e0080
39  
-f80001b1
  39
+f80001b7
40 40
 e0000069
41 41
 98000000
42 42
 78001000
@@ -44,7 +44,7 @@ e0000069
44 44
 581d0000
45 45
 f8000014
46 46
 5b9e0080
47  
-f80001a9
  47
+f80001af
48 48
 e0000061
49 49
 98000000
50 50
 78001000
@@ -52,7 +52,7 @@ e0000061
52 52
 581d0000
53 53
 f800000c
54 54
 5b9e0080
55  
-f80001a1
  55
+f80001a7
56 56
 e0000059
57 57
 98000000
58 58
 78001000
@@ -60,7 +60,7 @@ e0000059
60 60
 581d0000
61 61
 f8000004
62 62
 5b9e0080
63  
-f8000199
  63
+f800019f
64 64
 e0000051
65 65
 3400ff64
66 66
 58010004
@@ -179,11 +179,17 @@ c3e00000
179 179
 34210004
180 180
 e3fffffd
181 181
 c3a00000
182  
-90400800
183  
-20210001
184  
-4420fffe
185  
-34010001
186  
-d0410000
  182
+78021000
  183
+38420fb8
  184
+28410000
  185
+28220000
  186
+20420002
  187
+4440fffe
  188
+78031000
  189
+38630fb8
  190
+28610000
  191
+34020002
  192
+58220000
187 193
 7801e000
188 194
 28210000
189 195
 b0200800
@@ -191,11 +197,11 @@ c3a00000
191 197
 7802e000
192 198
 58410000
193 199
 78021000
194  
-38420f90
  200
+38420fb8
195 201
 28410000
196 202
 28220000
197  
-20420002
198  
-5c40fffe
  203
+20420001
  204
+4440fffe
199 205
 c3a00000
200 206
 b8201000
201 207
 3421ff9f
@@ -216,7 +222,7 @@ c3a00000
216 222
 3441ffc9
217 223
 c3a00000
218 224
 78041000
219  
-38840fe0
  225
+3884100c
220 226
 e000000d
221 227
 40250000
222 228
 3463ffff
@@ -307,7 +313,7 @@ c3a00000
307 313
 b8205800
308 314
 29620084
309 315
 78011000
310  
-38210fd8
  316
+38211004
311 317
 20420007
312 318
 b4220800
313 319
 10230000
@@ -317,7 +323,7 @@ b4220800
317 323
 14640004
318 324
 30410000
319 325
 78011000
320  
-38210fe0
  326
+3821100c
321 327
 2063000f
322 328
 2084000f
323 329
 b4242000
@@ -368,7 +374,7 @@ c3a00000
368 374
 780d1000
369 375
 780b1000
370 376
 39ad1804
371  
-396b0f98
  377
+396b0fc4
372 378
 3410002b
373 379
 34010024
374 380
 fbffff49
@@ -392,7 +398,7 @@ b56c6000
392 398
 fbffff37
393 399
 11810000
394 400
 fbffff35
395  
-fbffff2b
  401
+fbffff25
396 402
 5c30ffe9
397 403
 2b9d0004
398 404
 2b8b001c
@@ -460,10 +466,10 @@ b4823800
460 466
 e0000002
461 467
 fbffff20
462 468
 78011000
463  
-38210fac
  469
+38210fd8
464 470
 e0000003
465 471
 78011000
466  
-38210fb0
  472
+38210fdc
467 473
 fbffffc3
468 474
 2b9d0004
469 475
 2b8b0008
@@ -488,33 +494,35 @@ c3a00000
488 494
 5b9b0008
489 495
 5b9d0004
490 496
 78021000
491  
-38420f90
  497
+38420fbc
492 498
 b8206800
493 499
 28410000
494 500
 78031000
495  
-38630f94
  501
+38630fc0
496 502
 58200000
497 503
 28610000
498 504
 28220000
499 505
 5c400004
500 506
 34020001
501 507
 58220000
502  
-fbfffeb7
  508
+fbfffeb1
503 509
 78081000
504  
-39080f90
  510
+39080fb8
505 511
 29010000
506 512
 28220000
507  
-20420002
508  
-5c40fffe
509  
-9040d800
  513
+20420001
  514
+4440fffe
  515
+78021000
  516
+38420fb8
  517
+28410000
  518
+283b0000
510 519
 78011000
511 520
 38211800
512 521
 10210000
513  
-237b0002
514  
-44220004
  522
+44200004
515 523
 b9a00800
516  
-fbffff2a
517  
-fbffff63
  524
+fbffff28
  525
+fbffff61
518 526
 78101000
519 527
 780c1000
520 528
 78171000
@@ -529,20 +537,20 @@ fbffff63
529 537
 398c1b28
530 538
 3af71800
531 539
 3ad61b2b
532  
-39ef0fb0
533  
-3ab50fb8
534  
-3a730fac
  540
+39ef0fdc
  541
+3ab50fe4
  542
+3a730fd8
535 543
 396b1e50
536 544
 39ce1e4c
537 545
 3a521e64
538 546
 32000000
539 547
 34190024
540 548
 34180023
541  
-fbfffe99
  549
+fbfffe91
542 550
 5c39ffff
543 551
 34110000
544 552
 34140000
545  
-fbfffe95
  553
+fbfffe8d
546 554
 b8201000
547 555
 4439fffc
548 556
 44380008
@@ -550,35 +558,35 @@ b681a000
550 558
 b5910800
551 559
 30220000
552 560
 36310001
553  
-3401031f
  561
+3403031f
554 562
 229400ff
555  
-4c31fff6
  563
+4c71fff6
556 564
 b5918800
557 565
 32200000
558 566
 5c58ffef
559  
-fbfffe87
  567
+fbfffe7f
560 568
 202100ff
561  
-fbfffe97
  569
+fbfffe95
562 570
 3c210004
563 571
 203100ff
564  
-fbfffe82
  572
+fbfffe7a
565 573
 202100ff
566  
-fbfffe92
  574
+fbfffe90
567 575
 b6210800
568 576
 202100ff
569 577
 46810004
570 578
 3401002d
571  
-fbfffe84
  579
+fbfffe82
572 580
 e3ffffe1
573 581
 3401002b
574  
-fbfffe81
  582
+fbfffe7f
575 583
 11820002
576 584
 3401003a
577 585
 5c410005
578 586
 11810000
579  
-fbfffe7c
580  
-11810001
581 587
 fbfffe7a
  588
+11810001
  589
+fbfffe78
582 590
 11830000
583 591
 34010001
584 592
 32e10000
@@ -625,7 +633,7 @@ e000000c
625 633
 5c610149
626 634
 e0000071
627 635
 b9a00800
628  
-fbfffeba
  636
+fbfffeb8
629 637
 e0000145
630 638
 b9a00800
631 639
 ba001000
@@ -641,7 +649,7 @@ e0000040
641 649
 5b810050
642 650
 3782004c
643 651
 37810050
644  
-fbfffe8a
  652
+fbfffe88
645 653
 4c010121
646 654
 2b810050
647 655
 10220000
@@ -651,43 +659,43 @@ fbfffe8a
651 659
 5c41011b
652 660
 37810050
653 661
 37820048
654  
-fbfffe80
  662
+fbfffe7e
655 663
 4c010117
656 664
 2b830048
657 665
 3401018f
658 666
 54610114
659 667
 2b81004c
660 668
 ba001000
661  
-fbfffe45
  669
+fbfffe43
662 670
 5c200124
663 671
 78011000
664  
-38210fb4
665  
-e000014a
  672
+38210fe0
  673
+e000014c
666 674
 34010000
667 675
 e0000002
668 676
 34010001
669  
-fbffff04
  677
+fbffff02
670 678
 e000011c
671 679
 78011000
672 680
 38211b29
673 681
 5b810050
674 682
 3782004c
675 683
 37810050
676  
-fbfffe6a
  684
+fbfffe68
677 685
 4c010101
678 686
 2b81004c
679 687
 ba001000
680 688
 34030004
681 689
 3c210002
682 690
 b5a10800
683  
-fbfffe2f
  691
+fbfffe2d
684 692
 e000010e
685 693
 78011000
686 694
 38211b29
687 695
 5b810050
688 696
 3782004c
689 697
 37810050
690  
-fbfffe5c
  698
+fbfffe5a
691 699
 4c0100f3
692 700
 2b810050
693 701
 3402003d
@@ -699,7 +707,7 @@ fbfffe5c
699 707
 34030004
700 708
 3c420002
701 709
 b5a21000
702  
-fbfffe2f
  710
+fbfffe2d
703 711
 e00000e3
704 712
 d1000000
705 713
 d2000000
@@ -712,16 +720,16 @@ d2600000
712 720
 34010044
713 721
 5c6100f3
714 722
 78011000
715  
-38210fac
716  
-fbfffeca
717  
-fbfffe9b
  723
+38210fd8
  724
+fbfffec8
  725
+fbfffe99
718 726
 e00000ee
719 727
 78011000
720 728
 38211b29
721 729
 5b810050
722 730
 3782004c
723 731
 37810050
724  
-fbfffe3a
  732
+fbfffe38
725 733
 4c010003
726 734
 2b81004c
727 735
 59a10080
@@ -742,7 +750,7 @@ e00000da
742 750
 5e2100c0
743 751
 37810050
744 752
 3782004c
745  
-fbfffe25
  753
+fbfffe23
746 754
 4c0100bc
747 755
 2b820050
748 756
 10410000
@@ -751,7 +759,7 @@ fbfffe25
751 759
 5c3100b7
752 760
 37810050
753 761
 37820048
754  
-fbfffe1c
  762
+fbfffe1a
755 763
 4c0100b3
756 764
 11820001
757 765
 34010032
@@ -928,11 +936,11 @@ e0000009
928 936
 3c840002
929 937
 e3ffffeb
930 938
 ba600800
931  
-e0000040
  939
+e0000042
932 940
 baa00800
933  
-e000003e
  941
+e0000040
934 942
 b9e00800
935  
-e000003c
  943
+e000003e
936 944
 7802e000
937 945
 34010001
938 946
 3842103c
@@ -941,17 +949,17 @@ e000000e
941 949
 78021000
942 950
 78031000
943 951
 38421b29
944  
-38630fbc
  952
+38630fe8
945 953
 40440000
946 954
 40610000
947 955
 5c810007
948 956
 78081000
949 957
 39081b31
950  
-4448002b
  958
+4448002d
951 959
 34420001
952 960
 34630001
953 961
 e3fffff8
954  
-fbfffdae
  962
+fbfffdac
955 963
 e3fffe5f
956 964
 d0600000
957 965
 34000000
@@ -963,12 +971,14 @@ d0800000
963 971
 34000000
964 972
 34000000
965 973
 34000000
966  
-5f600003
967  
-34010002
968  
-d0410000
969 974
 78031000
970  
-38630f90
  975
+38630fb8
971 976
 28610000
  977
+78081000
  978
+23620004
  979
+39080fbc
  980
+58220000
  981
+29010000
972 982
 34020001
973 983
 58220000
974 984
 2b9d0004
@@ -991,10 +1001,11 @@ d0410000
991 1001
 379c0050
992 1002
 c3a00000
993 1003
 78011000
994  
-38210fc8
995  
-fbfffdb3
996  
-e3ffffd6
997  
-e000000c
  1004
+38210ff4
  1005
+fbfffdaf
  1006
+e3ffffd4
  1007
+e0000008
  1008
+e0000010
998 1009
 e0001030
999 1010
 30313233
1000 1011
 34353637
@@ -1019,18 +1030,7 @@ e0001030
1019 1030
 38396162
1020 1031
 63646566
1021 1032
 00000000
1022  
-02ef8670
1023  
-00000000
1024  
-00000000
1025  
-00000000
1026  
-00000000
1027  
-00000000
1028  
-00000000
1029  
-00000000
1030  
-00000000
1031  
-00000000
1032  
-00000000
1033  
-00000000
  1033
+69f0c80b
1034 1034
 00000000
1035 1035
 00000000
1036 1036
 00000000
57  cores/uart/doc/uart.tex
@@ -34,21 +34,68 @@ \section{Registers}
34 34
 \hline
35 35
 \bf{Offset} & \bf{Read/Write} & \bf{Default} & \bf{Description} \\
36 36
 \hline
37  
-0x0 & RW & 0x00 & Data register. Received bytes and bytes to transmit are read/written from/to this register. \\
  37
+0x00 & RW & 0x00 & Data register. Received bytes and bytes to transmit are read/written from/to this register. \\
38 38
 \hline
39  
-0x4 & RW & for default bitrate & Divisor register (for bitrate selection). \\
  39
+0x04 & RW & for default bitrate & Divisor register (for bitrate selection). \\
  40
+\hline
  41
+0x08 & R, W1C & 0x01 & Status and event register. Events are cleared by writing 1. \\
  42
+\hline
  43
+0x0c & RW & 0x00 & Control register. \\
  44
+\hline
  45
+0x10 & RW & configurable & Debug register. \\
40 46
 \hline
41 47
 \end{tabularx}\\
42 48
 
  49
+\subsection{Status and event register, offset 0x08}
  50
+\begin{tabularx}{\textwidth}{|l|l|l|X|}
  51
+\hline
  52
+\bf Bits & \bf Access & \bf Default & \bf Description \\
  53
+\hline
  54
+0 & R & 1 & (Transmit Holding Register Empty). If this bit is set, the transmit holding register is empty, eg. transmission is finished. \\
  55
+\hline
  56
+1 & R, W1C & 0 & (RX Event). See below. \\
  57
+\hline
  58
+2 & R, W1C & 0 & (TX Event). See below. \\
  59
+\hline
  60
+\end{tabularx}
  61
+
  62
+\subsection{Control register, offset 0x0c}
  63
+\begin{tabularx}{\textwidth}{|l|l|l|X|}
  64
+\hline
  65
+\bf Bits & \bf Access & \bf Default & \bf Description \\
  66
+\hline
  67
+0 & RW & 1 & (RX IRQ Enable). If this bit is set, a pending RX event will assert the interrupt output. \\
  68
+\hline
  69
+1 & RW & 1 & (TX IRQ Enable). If this bit is set, a pending TX event will assert the interrupt output. \\
  70
+\hline
  71
+2 & RW & 1 & (THRU). If this bit is set, MIDI thru mode is enabled. \\
  72
+\hline
  73
+\end{tabularx}
  74
+
  75
+\subsection{Debug control register, offset 0x10}
  76
+\begin{tabularx}{\textwidth}{|l|l|l|X|}
  77
+\hline
  78
+\bf Bits & \bf Access & \bf Default & \bf Description \\
  79
+\hline
  80
+0 & RW & 1 & (Break Enable). If this bit is set and the UART core receives a BREAK symbol, the break output will be pulsed and this bit is cleared automatically. \\
  81
+\hline
  82
+\end{tabularx}
  83
+
43 84
 \section{Interrupts}
44  
-The core has two active-high edge-sensitive interrupts outputs.
  85
+The core has one active-high level-sensitive interrupt output.
  86
+
  87
+Whenever an event bit is set and the corresponding event is enabled in the control register, the interrupt output is asserted.
45 88
 
46  
-The ``RX'' interrupt is sent whenever a new character is received. The CPU should then read the data register immediately. If a new character is sent before the CPU has had time to read it, the first character will be lost.
  89
+\section{Events}
  90
+The ``RX'' event is sent whenever a new character is received. The CPU should then read the data register immediately. If a new character is sent before the CPU has had time to read it, the first character will be lost.
47 91
 
48 92
 The ``TX'' interrupt is sent as soon as the UART finished transmitting a character. When the CPU has written to the data register, it must wait for the interrupt before writing again.
49 93
 
  94
+\section{MIDI thru mode}
  95
+TBD.
  96
+
50 97
 \section{Using the core}
51  
-Connect the CSR signals and the interrupts to the system bus and the interrupt controller. The \verb!uart_tx! and \verb!uart_rx! signals should go to the FPGA pads. You must also provide the desired default baudrate and the system clock frequency in Hz using the parameters.
  98
+Connect the CSR signals and the interrupt to the system bus and the interrupt controller. The \verb!uart_tx! and \verb!uart_rx! signals should go to the FPGA pads. You must also provide the desired default baudrate and the system clock frequency in Hz using the parameters. The \verb!break!  signal may be connected to your CPU debug unit to raise an exception on BREAK.
52 99
 
53 100
 \section*{Copyright notice}
54 101
 Copyright \copyright 2007-2010 S\'ebastien Bourdeauducq. \\
72  cores/uart/rtl/uart.v
@@ -29,8 +29,7 @@ module uart #(
29 29
 	input [31:0] csr_di,
30 30
 	output reg [31:0] csr_do,
31 31
 
32  
-	output rx_irq,
33  
-	output tx_irq,
  32
+	output irq,
34 33
 
35 34
 	input uart_rx,
36 35
 	output uart_tx,
@@ -55,58 +54,85 @@ uart_transceiver transceiver(
55 54
 	.divisor(divisor),
56 55
 
57 56
 	.rx_data(rx_data),
58  
-	.rx_done(rx_irq),
  57
+	.rx_done(rx_done),
59 58
 
60 59
 	.tx_data(tx_data),
61 60
 	.tx_wr(tx_wr),
62  
-	.tx_done(tx_irq),
  61
+	.tx_done(tx_done),
63 62
 
64 63
 	.break(break_transceiver)
65 64
 );
66 65
 
67  
-assign uart_tx = thru ? uart_rx : uart_tx_transceiver;
  66
+assign uart_tx = thru_en ? uart_rx : uart_tx_transceiver;
68 67
 assign break = break_en & break_transceiver;
69 68
 
70 69
 /* CSR interface */
71 70
 wire csr_selected = csr_a[13:10] == csr_addr;
72 71
 
  72
+assign irq = (tx_event & tx_irq_en) | (rx_event & rx_irq_en);
  73
+
73 74
 assign tx_data = csr_di[7:0];
74  
-assign tx_wr = csr_selected & csr_we & (csr_a[1:0] == 2'b00);
  75
+assign tx_wr = csr_selected & csr_we & (csr_a[2:0] == 3'b000);
75 76
 
76 77
 parameter default_divisor = clk_freq/baud/16;
77 78
 
78  
-reg thru;
  79
+reg thru_en;
79 80
 reg break_en;
80  
-reg tx_pending;
  81
+reg tx_irq_en;
  82
+reg rx_irq_en;
  83
+reg rx_event;
  84
+reg tx_event;
  85
+reg thre;
81 86
 
82 87
 always @(posedge sys_clk) begin
83 88
 	if(sys_rst) begin
84 89
 		divisor <= default_divisor;
85 90
 		csr_do <= 32'd0;
86  
-		thru <= 1'b0;
  91
+		thru_en <= 1'b0;
87 92
 		break_en <= break_en_default;
88  
-		tx_pending <= 1'b0;
  93
+		rx_irq_en <= 1'b0;
  94
+		tx_irq_en <= 1'b0;
  95
+		tx_event <= 1'b0;
  96
+		rx_event <= 1'b0;
  97
+		thre <= 1'b1;
89 98
 	end else begin
90 99
 		csr_do <= 32'd0;
91 100
 		if(break)
92 101
 			break_en <= 1'b0;
93  
-		if(tx_irq)
94  
-			tx_pending <= 1'b0;
  102
+		if(tx_done) begin
  103
+			tx_event <= 1'b1;
  104
+			thre <= 1'b1;
  105
+		end
95 106
 		if(tx_wr)
96  
-			tx_pending <= 1'b1;
  107
+			thre <= 1'b0;
  108
+		if(rx_done) begin
  109
+			rx_event <= 1'b1;
  110
+		end
97 111
 		if(csr_selected) begin
98  
-			case(csr_a[1:0])
99  
-				2'b00: csr_do <= rx_data;
100  
-				2'b01: csr_do <= divisor;
101  
-				2'b10: csr_do <= thru;
102  
-				2'b11: csr_do <= {tx_pending, break_en};
  112
+			case(csr_a[2:0])
  113
+				3'b000: csr_do <= rx_data;
  114
+				3'b001: csr_do <= divisor;
  115
+				3'b010: csr_do <= {tx_event, rx_event, thre};
  116
+				3'b011: csr_do <= {thru_en, tx_irq_en, rx_irq_en};
  117
+				3'b100: csr_do <= {break_en};
103 118
 			endcase
104 119
 			if(csr_we) begin
105  
-				case(csr_a[1:0])
106  
-					2'b00:; /* handled by transceiver */
107  
-					2'b01: divisor <= csr_di[15:0];
108  
-					2'b10: thru <= csr_di[0];
109  
-					2'b11: break_en <= csr_di[0];
  120
+				case(csr_a[2:0])
  121
+					3'b000:; /* handled by transceiver */
  122
+					3'b001: divisor <= csr_di[15:0];
  123
+					3'b010: begin
  124
+						/* write one to clear */
  125
+						if(csr_di[1])
  126
+							rx_event <= 1'b0;
  127
+						if(csr_di[2])
  128
+							tx_event <= 1'b0;
  129
+					end
  130
+					3'b011: begin
  131
+						rx_irq_en <= csr_di[0];
  132
+						tx_irq_en <= csr_di[1];
  133
+						thru_en <= csr_di[2];
  134
+					end
  135
+					3'b100: break_en <= csr_di[0];
110 136
 				endcase
111 137
 			end
112 138
 		end
6  software/bios/isr.c
@@ -28,10 +28,8 @@ void isr()
28 28
 
29 29
 	irqs = irq_pending() & irq_getmask();
30 30
 
31  
-	if(irqs & IRQ_UARTRX)
32  
-		uart_isr_rx();
33  
-	if(irqs & IRQ_UARTTX)
34  
-		uart_isr_tx();
  31
+	if(irqs & IRQ_UART)
  32
+		uart_isr();
35 33
 		
36 34
 	if(irqs & IRQ_TMU)
37 35
 		tmu_isr();
6  software/demo/isr.c
@@ -35,10 +35,8 @@ void isr()
35 35
 
36 36
 	irqs = irq_pending() & irq_getmask();
37 37
 
38  
-	if(irqs & IRQ_UARTRX)
39  
-		uart_isr_rx();
40  
-	if(irqs & IRQ_UARTTX)
41  
-		uart_isr_tx();
  38
+	if(irqs & IRQ_UART)
  39
+		uart_isr();
42 40
 
43 41
 	if(irqs & IRQ_TIMER0)
44 42
 		time_isr();
10  software/demo/shell.c
@@ -780,16 +780,16 @@ static void irtest()
780 780
 static void midiprint()
781 781
 {
782 782
 	unsigned int r;
783  
-	if(irq_pending() & IRQ_MIDIRX) {
  783
+	if(CSR_MIDI_STAT & MIDI_STAT_RX_EVT) {
784 784
 		r = CSR_MIDI_RXTX;
785  
-		irq_ack(IRQ_MIDIRX);
  785
+		CSR_MIDI_STAT = MIDI_STAT_RX_EVT;
786 786
 		printf("RX: %02x\n", r);
787 787
 	}
788 788
 }
789 789
 
790 790
 static void midirx()
791 791
 {
792  
-	irq_ack(IRQ_MIDIRX);
  792
+	CSR_MIDI_STAT = MIDI_STAT_RX_EVT;
793 793
 	while(!readchar_nonblock()) midiprint();
794 794
 }
795 795
 
@@ -797,9 +797,9 @@ static void midisend(int c)
797 797
 {
798 798
 	printf("TX: %02x\n", c);
799 799
 	CSR_MIDI_RXTX = c;
800  
-	while(!(irq_pending() & IRQ_MIDITX));
  800
+	while(!(CSR_MIDI_STAT & MIDI_STAT_TX_EVT));
801 801
 	printf("TX done\n");
802  
-	irq_ack(IRQ_MIDITX);
  802
+	CSR_MIDI_STAT = MIDI_STAT_TX_EVT;
803 803
 	midiprint();
804 804
 }
805 805
 
33  software/gdbstub/gdbstub.c
@@ -109,17 +109,16 @@ static int memcmp(const void *cs, const void *ct, size_t count)
109 109
 
110 110
 static char get_debug_char(void)
111 111
 {
112  
-    while (!(irq_pending() & IRQ_UARTRX));
113  
-    irq_ack(IRQ_UARTRX);
  112
+    while (!(CSR_UART_STAT & UART_STAT_RX_EVT));
  113
+    CSR_UART_STAT = UART_STAT_RX_EVT;
114 114
     return (char)CSR_UART_RXTX;
115 115
 }
116 116
 
117 117
 static void put_debug_char(char c)
118 118
 {
119 119
     CSR_UART_RXTX = c;
120  
-    /* Blocking on UART pending bit is intended here! Have a
121  
-     * look at the end of handle_exception() too. */
122  
-    while (CSR_UART_BREAK & UART_TX_PENDING);
  120
+    /* loop on THRE, TX_EVT must not be cleared */
  121
+    while (!(CSR_UART_STAT & UART_STAT_THRE));
123 122
 }
124 123
 
125 124
 /*
@@ -671,8 +670,8 @@ static void cmd_query(void)
671 670
  */
672 671
 void handle_exception(unsigned int *registers)
673 672
 {
674  
-    int irq;
675  
-    
  673
+    unsigned int stat;
  674
+
676 675
     /*
677 676
      * make sure break is disabled.
678 677
      * we can enter the stub with break enabled when the application calls it.
@@ -681,7 +680,7 @@ void handle_exception(unsigned int *registers)
681 680
      * applications should disable debug exceptions before jumping to debug
682 681
      * ROM.
683 682
      */
684  
-    CSR_UART_BREAK = 0;
  683
+    CSR_UART_DEBUG = 0;
685 684
 
686 685
     /* clear BSS there was a board reset */
687 686
     if (!CSR_DBG_SCRATCHPAD) {
@@ -689,11 +688,11 @@ void handle_exception(unsigned int *registers)
689 688
         clear_bss();
690 689
     }
691 690
 
692  
-    /* wait until TX transaction is finished */
693  
-    while (CSR_UART_BREAK & UART_TX_PENDING);
694  
-
695  
-    /* remember if irq was set */
696  
-    irq = irq_pending() & IRQ_UARTTX;
  691
+    /* wait until TX transaction is finished. If there was a transmission in
  692
+     * progress, the event bit will be set. In this case, the gdbstub won't clear
  693
+     * it after it is terminated. */
  694
+    while(!(CSR_UART_STAT & UART_STAT_THRE));
  695
+    stat = CSR_UART_STAT;
697 696
 
698 697
     /* reply to host that an exception has occured */
699 698
     if (gdb_connected) {
@@ -768,11 +767,9 @@ void handle_exception(unsigned int *registers)
768 767
 out:
769 768
     flush_cache();
770 769
 
771  
-    /* ack TX IRQ only if it wasn't set before */
772  
-    if (!irq) {
773  
-        irq_ack(IRQ_UARTTX);
774  
-    }
  770
+    /* clear TX event if there was no transmission in progress */
  771
+    CSR_UART_STAT = stat & UART_STAT_TX_EVT;
775 772
 
776 773
     /* reenable break */
777  
-    CSR_UART_BREAK = UART_BREAK_EN;
  774
+    CSR_UART_DEBUG = UART_DEBUG_BREAK_EN;
778 775
 }
3  software/include/base/uart.h
@@ -19,8 +19,7 @@
19 19
 #define __UART_H
20 20
 
21 21
 void uart_init();
22  
-void uart_isr_rx();
23  
-void uart_isr_tx();
  22
+void uart_isr();
24 23
 void uart_force_sync(int f);
25 24
 
26 25
 void uart_write(char c);
34  software/include/hw/interrupts.h
@@ -18,23 +18,21 @@
18 18
 #ifndef __HW_INTERRUPTS_H
19 19
 #define __HW_INTERRUPTS_H
20 20
 
21  
-#define IRQ_UARTRX		(0x00000001) /* 0 */
22  
-#define IRQ_UARTTX		(0x00000002) /* 1 */
23  
-#define IRQ_GPIO		(0x00000004) /* 2 */
24  
-#define IRQ_TIMER0		(0x00000008) /* 3 */
25  
-#define IRQ_TIMER1		(0x00000010) /* 4 */
26  
-#define IRQ_AC97CRREQUEST	(0x00000020) /* 5 */
27  
-#define IRQ_AC97CRREPLY		(0x00000040) /* 6 */
28  
-#define IRQ_AC97DMAR		(0x00000080) /* 7 */
29  
-#define IRQ_AC97DMAW		(0x00000100) /* 8 */
30  
-#define IRQ_PFPU		(0x00000200) /* 9 */
31  
-#define IRQ_TMU			(0x00000400) /* 10 */
32  
-#define IRQ_ETHRX		(0x00000800) /* 11 */
33  
-#define IRQ_ETHTX		(0x00001000) /* 12 */
34  
-#define IRQ_VIDEOIN		(0x00002000) /* 13 */
35  
-#define IRQ_MIDIRX		(0x00004000) /* 14 */
36  
-#define IRQ_MIDITX		(0x00008000) /* 15 */
37  
-#define IRQ_IR			(0x00010000) /* 16 */
38  
-#define IRQ_USB			(0x00020000) /* 17 */
  21
+#define IRQ_UART		(0x00000001) /* 0 */
  22
+#define IRQ_GPIO		(0x00000002) /* 1 */
  23
+#define IRQ_TIMER0		(0x00000004) /* 2 */
  24
+#define IRQ_TIMER1		(0x00000008) /* 3 */
  25
+#define IRQ_AC97CRREQUEST	(0x00000010) /* 4 */
  26
+#define IRQ_AC97CRREPLY		(0x00000020) /* 5 */
  27
+#define IRQ_AC97DMAR		(0x00000040) /* 6 */
  28
+#define IRQ_AC97DMAW		(0x00000080) /* 7 */
  29
+#define IRQ_PFPU		(0x00000100) /* 8 */
  30
+#define IRQ_TMU			(0x00000200) /* 9 */
  31
+#define IRQ_ETHRX		(0x00000400) /* 10 */
  32
+#define IRQ_ETHTX		(0x00000800) /* 11 */
  33
+#define IRQ_VIDEOIN		(0x00001000) /* 12 */
  34
+#define IRQ_MIDI		(0x00002000) /* 13 */
  35
+#define IRQ_IR			(0x00004000) /* 14 */
  36
+#define IRQ_USB			(0x00008000) /* 15 */
39 37
 
40 38
 #endif /* __HW_INTERRUPTS_H */
11  software/include/hw/midi.h
@@ -22,6 +22,15 @@
22 22
 
23 23
 #define CSR_MIDI_RXTX 		MMPTR(0xe000b000)
24 24
 #define CSR_MIDI_DIVISOR	MMPTR(0xe000b004)
25  
-#define CSR_MIDI_THRU		MMPTR(0xe000b008)
  25
+#define CSR_MIDI_STAT		MMPTR(0xe000b008)
  26
+#define CSR_MIDI_CTRL		MMPTR(0xe000b00c)
  27
+
  28
+#define MIDI_STAT_THRE		(0x1)
  29
+#define MIDI_STAT_RX_EVT	(0x2)
  30
+#define MIDI_STAT_TX_EVT	(0x4)
  31
+
  32
+#define MIDI_CTRL_RX_INT	(0x1)
  33
+#define MIDI_CTRL_TX_INT	(0x2)
  34
+#define MIDI_CTRL_THRU		(0x4)
26 35
 
27 36
 #endif /* __HW_MIDI_H */
16  software/include/hw/uart.h
@@ -22,12 +22,18 @@
22 22
 
23 23
 #define CSR_UART_RXTX 		MMPTR(0xe0000000)
24 24
 #define CSR_UART_DIVISOR	MMPTR(0xe0000004)
25  
-#define CSR_UART_THRU		MMPTR(0xe0000008)
26  
-#define CSR_UART_BREAK		MMPTR(0xe000000c)
  25
+#define CSR_UART_STAT		MMPTR(0xe0000008)
  26
+#define CSR_UART_CTRL		MMPTR(0xe000000c)
  27
+#define CSR_UART_DEBUG		MMPTR(0xe0000010)
27 28
 
28  
-#define UART_THRU		(0x1)
  29
+#define UART_STAT_THRE		(0x1)
  30
+#define UART_STAT_RX_EVT	(0x2)
  31
+#define UART_STAT_TX_EVT	(0x4)
29 32
 
30  
-#define UART_BREAK_EN		(0x1)
31  
-#define UART_TX_PENDING		(0x2)
  33
+#define UART_CTRL_RX_INT	(0x1)
  34
+#define UART_CTRL_TX_INT	(0x2)
  35
+#define UART_CTRL_THRU		(0x4)
  36
+
  37
+#define UART_DEBUG_BREAK_EN	(0x1)
32 38
 
33 39
 #endif /* __HW_UART_H */
4  software/libbase/console.c
@@ -65,7 +65,7 @@ int puts(const char *s)
65 65
 	unsigned int oldmask;
66 66
 
67 67
 	oldmask = irq_getmask();
68  
-	irq_setmask(IRQ_UARTRX); // HACK: prevent UART data loss
  68
+	irq_setmask(IRQ_UART); // HACK: prevent UART data loss
69 69
 
70 70
 	while(*s) {
71 71
 		writechar(*s);
@@ -82,7 +82,7 @@ void putsnonl(const char *s)
82 82
 	unsigned int oldmask;
83 83
 
84 84
 	oldmask = irq_getmask();
85  
-	irq_setmask(IRQ_UARTRX); // HACK: prevent UART data loss
  85
+	irq_setmask(IRQ_UART); // HACK: prevent UART data loss
86 86
 	
87 87
 	while(*s) {
88 88
 		writechar(*s);
67  software/libbase/uart.c
@@ -34,11 +34,36 @@ static char rx_buf[UART_RINGBUFFER_SIZE_RX];
34 34
 static volatile unsigned int rx_produce;
35 35
 static volatile unsigned int rx_consume;
36 36
 
37  
-void uart_isr_rx()
  37
+#define UART_RINGBUFFER_SIZE_TX 131072
  38
+#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1)
  39
+
  40
+static char tx_buf[UART_RINGBUFFER_SIZE_TX];
  41
+static unsigned int tx_produce;
  42
+static unsigned int tx_consume;
  43
+static volatile int tx_cts;
  44
+
  45
+static int force_sync;
  46
+
  47
+
  48
+void uart_isr()
38 49
 {
39  
-	irq_ack(IRQ_UARTRX);
40  
-	rx_buf[rx_produce] = CSR_UART_RXTX;
41  
-	rx_produce = (rx_produce + 1) & UART_RINGBUFFER_MASK_RX;
  50
+	unsigned int stat = CSR_UART_STAT;
  51
+
  52
+	if(stat & UART_STAT_RX_EVT) {
  53
+		rx_buf[rx_produce] = CSR_UART_RXTX;
  54
+		rx_produce = (rx_produce + 1) & UART_RINGBUFFER_MASK_RX;
  55
+	}
  56
+
  57
+	if(stat & UART_STAT_TX_EVT) {
  58
+		if(tx_produce != tx_consume) {
  59
+			CSR_UART_RXTX = tx_buf[tx_consume];
  60
+			tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX;
  61
+		} else
  62
+			tx_cts = 1;
  63
+	}
  64
+
  65
+	CSR_UART_STAT = stat;
  66
+	irq_ack(IRQ_UART);
42 67
 }
43 68
 
44 69
 /* Do not use in interrupt handlers! */
@@ -57,36 +82,16 @@ int uart_read_nonblock()
57 82
 	return (rx_consume != rx_produce);
58 83
 }
59 84
 
60  
-#define UART_RINGBUFFER_SIZE_TX 131072
61  
-#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1)
62  
-
63  
-static char tx_buf[UART_RINGBUFFER_SIZE_TX];
64  
-static unsigned int tx_produce;
65  
-static unsigned int tx_consume;
66  
-static volatile int tx_cts;
67  
-
68  
-static int force_sync;
69  
-
70  
-void uart_isr_tx()
71  
-{
72  
-	irq_ack(IRQ_UARTTX);
73  
-	if(tx_produce != tx_consume) {
74  
-		CSR_UART_RXTX = tx_buf[tx_consume];
75  
-		tx_consume = (tx_consume + 1) & UART_RINGBUFFER_MASK_TX;
76  
-	} else
77  
-		tx_cts = 1;
78  
-}
79  
-
80 85
 void uart_write(char c)
81 86
 {
82 87
 	unsigned int oldmask;
83 88
 	
84 89
 	oldmask = irq_getmask();
85 90
 	irq_setmask(0);
  91
+
86 92
 	if(force_sync) {
87 93
 		CSR_UART_RXTX = c;
88  
-		while(!(irq_pending() & IRQ_UARTTX));
89  
-		irq_ack(IRQ_UARTTX);
  94
+		while(!(CSR_UART_STAT & UART_STAT_THRE));
90 95
 	} else {
91 96
 		if(tx_cts) {
92 97
 			tx_cts = 0;
@@ -109,10 +114,16 @@ void uart_init()
109 114
 	tx_consume = 0;
110 115
 	tx_cts = 1;
111 116
 
112  
-	irq_ack(IRQ_UARTRX|IRQ_UARTTX);
  117
+	irq_ack(IRQ_UART);
  118
+
  119
+	/* ack any events */
  120
+	CSR_UART_STAT = CSR_UART_STAT;
  121
+
  122
+	/* enable interrupts */
  123
+	CSR_UART_CTRL = UART_CTRL_TX_INT | UART_CTRL_RX_INT;
113 124
 
114 125
 	mask = irq_getmask();
115  
-	mask |= IRQ_UARTRX|IRQ_UARTTX;
  126
+	mask |= IRQ_UART;
116 127
 	irq_setmask(mask);
117 128
 }
118 129
 
4  software/libhal/vga.c
@@ -360,10 +360,10 @@ static void scroll_callback(struct tmu_td *td)
360 360
 	unsigned int oldmask;
361 361
 	unsigned int ie;
362 362
 	
363  
-	/* HACK: allow nested UART RX interrupts to prevent data loss */
  363
+	/* HACK: allow nested UART interrupts to prevent data loss */
364 364
 	ie = irq_getie();
365 365
 	oldmask = irq_getmask();
366  
-	irq_setmask(IRQ_UARTRX);
  366
+	irq_setmask(IRQ_UART);
367 367
 	irq_enable(1);
368 368
 	
369 369
 	flush_cpu_dcache();
39  software/libhpdmc/libhpdmc.S
@@ -342,16 +342,18 @@ boot:
342 342
  *
343 343
  * inputs:	none
344 344
  * outputs:	r1 - character
345  
- * clobbers:	r1
  345
+ * clobbers:	r1, r2
346 346
  */
347 347
 getkey:
348  
-	rcsr	r1, IP
349  
-	andi	r1, r1, IRQ_UARTRX
350  
-	be	r1, r0, getkey
351  
-	wcsr	IP, r1
352  
-	mvhi	r1, hi(CSR_UART_RXTX)
353  
-	ori	r1, r1, lo(CSR_UART_RXTX)
354  
-	lw	r1, (r1+0)
  348
+	mvhi	r2, hi(CSR_UART_RXTX)
  349
+	ori	r2, r2, lo(CSR_UART_RXTX)
  350
+getkeywait:
  351
+	lw	r1, (r2+8)
  352
+	andi	r1, r1, UART_STAT_RX_EVT
  353
+	be	r1, r0, getkeywait
  354
+	mvi	r1, UART_STAT_RX_EVT
  355
+	sw	(r2+8), r1
  356
+	lw	r1, (r2+0)
355 357
 	ret
356 358
 #endif /* FEAT_MANUAL_CALIBRATION */
357 359
 
@@ -416,8 +418,8 @@ printint:
416 418
 	mvu	r3, '-'
417 419
 	sw	(r2+0), r3
418 420
 writeintwait0:
419  
-	rcsr	r3, IP
420  
-	andi	r3, r3, IRQ_UARTTX
  421
+	lw	r3, (r2+8)
  422
+	andi	r3, r3, UART_STAT_THRE
421 423
 	be	r3, r0, writeintwait0
422 424
 	wcsr	IP, r3
423 425
 
@@ -428,8 +430,8 @@ positive:
428 430
 	addi	r3, r3, '0'
429 431
 	sw	(r2+0), r3
430 432
 writeintwait1:
431  
-	rcsr	r3, IP
432  
-	andi	r3, r3, IRQ_UARTTX
  433
+	lw	r3, (r2+8)
  434
+	andi	r3, r3, UART_STAT_THRE
433 435
 	be	r3, r0, writeintwait1
434 436
 	wcsr	IP, r3
435 437
 	
@@ -439,16 +441,16 @@ writeintwait1:
439 441
 	addi	r3, r3, '0'
440 442
 	sw	(r2+0), r3
441 443
 writeintwait2:
442  
-	rcsr	r3, IP
443  
-	andi	r3, r3, IRQ_UARTTX
  444
+	lw	r3, (r2+8)
  445
+	andi	r3, r3, UART_STAT_THRE
444 446
 	be	r3, r0, writeintwait2
445 447
 	wcsr	IP, r3
446 448
 	
447 449
 	addi	r3, r1, '0'
448 450
 	sw	(r2+0), r3
449 451
 writeintwait3:
450  
-	rcsr	r3, IP
451  
-	andi	r3, r3, IRQ_UARTTX
  452
+	lw	r3, (r2+8)
  453
+	andi	r3, r3, UART_STAT_THRE
452 454
 	be	r3, r0, writeintwait3
453 455
 	wcsr	IP, r3
454 456
 
@@ -468,10 +470,9 @@ writeloop:
468 470
 	be	r3, r0, print_endloop
469 471
 	sw	(r2+0), r3
470 472
 writewait:
471  
-	rcsr	r3, IP
472  
-	andi	r3, r3, IRQ_UARTTX
  473
+	lw	r3, (r2+8)
  474
+	andi	r3, r3, UART_STAT_THRE
473 475
 	be	r3, r0, writewait
474  
-	wcsr	IP, r3
475 476
 	addi	r1, r1, 1
476 477
 	bi	writeloop
477 478
 print_endloop:

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