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  • 12 commits
  • 27 files changed
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  • 3 contributors
Showing with 899 additions and 347 deletions.
  1. +77 −34 LICENSE.LATTICE
  2. +35 −14 boards/milkymist-one/rtl/lm32_include.v
  3. +1 −1  boards/milkymist-one/rtl/system.v
  4. +1 −1  boards/milkymist-one/synthesis/common.mak
  5. +2 −0  cores/lm32/CHANGELOG
  6. +35 −14 cores/lm32/rtl/lm32_adder.v
  7. +35 −14 cores/lm32/rtl/lm32_addsub.v
  8. +61 −22 cores/lm32/rtl/lm32_cpu.v
  9. +35 −14 cores/lm32/rtl/lm32_dcache.v
  10. +35 −14 cores/lm32/rtl/lm32_debug.v
  11. +35 −14 cores/lm32/rtl/lm32_decoder.v
  12. +36 −15 cores/lm32/rtl/lm32_functions.v
  13. +35 −14 cores/lm32/rtl/lm32_icache.v
  14. +64 −16 cores/lm32/rtl/lm32_instruction_unit.v
  15. +35 −14 cores/lm32/rtl/lm32_interrupt.v
  16. +35 −14 cores/lm32/rtl/lm32_jtag.v
  17. +35 −14 cores/lm32/rtl/lm32_load_store_unit.v
  18. +35 −14 cores/lm32/rtl/lm32_logic_op.v
  19. +35 −14 cores/lm32/rtl/lm32_mc_arithmetic.v
  20. +35 −14 cores/lm32/rtl/lm32_multiplier.v
  21. +35 −14 cores/lm32/rtl/lm32_ram.v
  22. +35 −14 cores/lm32/rtl/lm32_shifter.v
  23. +51 −14 cores/lm32/rtl/lm32_top.v
  24. +17 −3 software/gdbstub/crt0.S
  25. +6 −4 software/gdbstub/gdbstub.c
  26. +1 −1  software/include/base/version.h
  27. +57 −26 tools/flterm.c
View
111 LICENSE.LATTICE
@@ -1,10 +1,11 @@
LATTICE SEMICONDUCTOR CORPORATION
-LatticeMico32 System License Agreement
+LatticeMico TM System License Agreement
This is a legal agreement between you, the end user, and Lattice Semiconductor
Corporation. By proceeding with the installation or use of the Software, you
agree to be bound by the terms of this Agreement. If you do not agree to the
-terms of this Agreement, do not use the Software, and promptly return the
+terms of this Agreement, do not use, download or install the Software, and if you
+have already obtained the Software from an authorized source, promptly return the
media package and all accompanying items (including written materials and
binders or other containers) to the place you obtained them for a full refund
of any applicable license fees.
@@ -13,7 +14,7 @@ Lattice Semiconductor Corporation ("Lattice") and the individual or entity
acquiring the Software ("Licensee") agree as follows:
1. DEFINITIONS
-"Software" means the LatticeMico32 System computer program(s) other than the
+"Software" means the LatticeMico System computer program(s) other than the
open source programs identified in Section 11 herein in machine-readable form
furnished to Licensee by Lattice, in whatever media and by whatever method,
which are enabled for use pursuant to Lattice's software protection mechanism,
@@ -143,23 +144,23 @@ Bureau of Industry and Security;
- that Licensee is not on the list of Specially Designated Nationals and
Blocked Persons maintained by the U.S. Department of the Treasury;
- that Licensee is not a citizen or resident of, or an agent of, Cuba, Iran,
-Iraq, North Korea, Libya, Sudan, or Syria, or any other country to which
+Iraq, North Korea, Sudan, or Syria, or any other country to which
export of the referenced Software is prohibited; and
- that Licensee is legally permitted, under all applicable export and
commerce control laws and regulations, to receive the referenced Software.
9. U.S. GOVERNMENT RESTRICTED RIGHTS
-The Software and any accompanying documentation are provided with RESTRICTED
-RIGHTS. Use, duplication, or disclosure by the Government is subject to
-restrictions as set forth in subparagraph (c)(1)(ii) of The Rights in
-Technical Data and Computer Software clause at DFARS 252.227-7013 or
-subparagraphs (c)(1) and (2) of Commercial Computer Software--Restricted
-Rights at 48 CFR 52.227-19, as applicable. Contractor/manufacturer is Lattice
-Semiconductor Corporation, 5555 NE Moore Court, Hillsboro, Oregon 97124 and
-its licensors.
+The Software and any accompanying documentation provided to agencies of the
+U.S. Government are "commercial computer software" and "commercial computer
+software documentation" pursuant to DFARS 227.7202 and FAR 12.212, and their
+successors. All use, reproduction, release, performance, display or disclosure
+of the Software and related documentation by or for the U.S. Government shall
+be in strict accordance with the terms and conditions of this Agreement.
+Contractor/manufacturer is Lattice Semiconductor Corporation, 5555 NE Moore
+Court, Hillsboro, Oregon 97124 and its licensors.
10. ADDITIONAL TERMS AND CONDITIONS APPLICABLE TO LATTICE PROGRAMMING HARDWARE
-Lattice programmers, ispDOWNLOAD® cables, and other hardware sold for use in
+Lattice programmers, ispDOWNLOADTM cables, and other hardware sold for use in
conjunction with Lattice software ("Programming Hardware") are designed and
intended for use solely with semiconductor components manufactured by Lattice
Semiconductor Corporation. Programming Hardware is warranted to meet Lattice
@@ -188,12 +189,15 @@ v. 1.0, a copy of which is attached hereto as Appendix A.
c. Certain open source code is licensed pursuant to the terms of the notice
attached hereto as Appendix B.
+d. Certain portion of the Software are licensed under the Mozilla Public License,
+Version 1.1. pursuant to the terms of the notice attached hereto as Appendix C.
+
12. OPEN SOURCE LICENSE AGREEMENT FOR OUTPUT FILES GENERATED BY THE
-LATTICEMICO32 SYSTEM
-By proceeding with the installation and use of the LatticeMico32 System, you
+LATTICEMICO SYSTEM
+By proceeding with the installation and use of the LatticeMico System, you
are agreeing to use the output files generated by it in accordance with the
terms of the Lattice Semiconductor Corporation Open Source License Agreement,
-a copy of which is attached hereto as Appendix C.
+a copy of which is attached hereto as Appendix D.
13. INFORMATION REGARDING PERSONAL DATA
If you downloaded this Software from our website, we have collected
@@ -205,7 +209,7 @@ you for certain information, including your name and contact information, as
part of the installation procedure.
Some of our Software comes bundled with software from third party providers,
-including Mentor Graphics Corporation and Synplicity, Inc. If you obtain a
+including Aldec, Inc. and Synopsys, Inc. If you obtain a
license key from us for such Software, we will provide your name, corporate
affiliation, address, phone number, fax number, and email address, along with
information about the software version you have chosen, to the appropriate
@@ -215,29 +219,36 @@ third party provider.
THIS AGREEMENT WILL BE GOVERNED BY THE LAWS OF THE STATE OF OREGON, WITHOUT
REGARD TO ITS CONFLICT OF LAWS PROVISIONS.
-Licensee may not sublicense, assign, or transfer the License or the Software.
-
The prevailing party in any legal action or arbitration arising out of this
-Agreement shall be entitled to reimbursement for reasonable attorneys fees
+Agreement shall be entitled to reimbursement for reasonable attorneys' fees
and expenses, in addition to any other rights and remedies such party may have.
-This Agreement is the entire agreement between the parties and supersedes any
-other communications or prior agreements, oral or written, regarding the
-Software.
+Lattice reserves the right in its sole discretion to discontinue third party
+software tools that come bundled with the Software at any time.
+
+Licensee may not sublicense, assign, or transfer this license or the Software.
+Any attempted assignment, transfer or sublicense by Licensee in violation of
+this provision shall be void. Subject to the foregoing, this Agreement shall
+be binding upon and inure to the benefit of the successors and permitted
+assigns of the parties.
+
+This Agreement is the entire agreement between the parties with respect to use
+of the Software and supersedes any other communications or prior agreements,
+oral or written, regarding the Software.
If any provision of this Agreement is held invalid, the remainder of the
Agreement shall continue in full force and effect.
Please direct all inquiries, in writing, to Lattice Semiconductor Corporation,
5555 N.E. Moore Court, Hillsboro, Oregon 97124.
-©2006-2008 Lattice Semiconductor Corporation. All rights reserved.
+(c)2006-2011 Lattice Semiconductor Corporation. All rights reserved.
Intellectual Property Notice
The software governed by this License Agreement is:
-Copyright ©, 1992-2008, Lattice Semiconductor Corporation, All Rights Reserved
+Copyright (c), 2006-2011, Lattice Semiconductor Corporation, All Rights Reserved
@@ -468,12 +479,32 @@ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
APPENDIX C
+The following terms only apply to the executable code version of the SeaMonkey
+program made available with the Software ("the Product"):
+
+The Product is subject to the Mozilla Public License, Version 1.1 (the "License");
+you may not use the Product except in compliance with this License. You may
+obtain a copy of the License at http://www.mozilla.org/MPL/
+
+The Product distributed under this license is distributed on an "AS IS" basis,
+WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
+specific language governing rights and limitations under the License.
+
+A source code version of the SeaMonkey program is available to you from:
+http://www.seamonkey-project.org/releases/1.0.1
+
+
+APPENDIX D
+
LATTICE SEMICONDUCTOR CORPORATION OPEN SOURCE LICENSE AGREEMENT
This is a legal agreement between You (Licensee, either a company or an
individual), and Lattice Semiconductor Corporation, the Provider (Licensor)
-of the Software. The Software subject to this Open Source License Agreement
-is the output files generated by the Provider's LatticeMico32 System. By
+of the Software. If a component covered by this Agreement can be
+included in the output files generated by the Provider's LatticeMico
+System or any other Provider source code generation tool, then Software
+refers to such output files that includes that component. Otherwise,
+Software refers to the component on a standalone basis. By
proceeding with the installation, modification, use or distribution in whole
or in part of Software that identifies itself as licensed under the Lattice
Semiconductor Corporation Open Source License Agreement, You agree to be
@@ -488,8 +519,8 @@ and warranty sections remain intact.
2. The Provider grants to You a personal, non-exclusive right to modify the
source code of the Software and incorporate it with other source code to
-create a Derivative Work. At Your discretion, You may distribute this
-Derivative Work in a form and under terms of Your choosing provided:
+create a Derivative Work (as defined below). At Your discretion, You may
+distribute this Derivative Work under terms of Your choosing provided:
- You arrange Your design such that the Derivative Work is an identifiable
module within Your overall design.
- You distribute the source code associated with the modules containing the
@@ -499,6 +530,13 @@ charge under a license agreement that contains these license terms.
and warranty sections remain intact.
- You clearly identify areas of the source code that You have modified.
+"Derivative Work" means a version of the Software in source code form that
+contains modifications or additions to the original source code and includes all
+Software files used to implement Your design. Derivative Work does not include
+identifiable modules within Your design that are not derived from the Software
+and that can be reasonably considered independent and separate modules from
+the Software.
+
3. The Provider grants to You a personal, non-exclusive right to use object
code created from the Software or a Derivative Work to physically implement
the design in devices such as a programmable logic devices or application
@@ -517,7 +555,7 @@ OF SUCH DAMAGES.
EXPRESSED, IMPLIED, STATUTORY, OR IN ANY OTHER PROVISION OF THIS AGREEMENT OR
COMMUNICATION WITH YOU, AND THE PROVIDER SPECIFICALLY DISCLAIMS ANY IMPLIED
WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR
-NON-INFRINGEMNT OF THIRD PARTY RIGHTS. THE PROVIDER DOES NOT WARRANT THAT USE
+NON-INFRINGEMENT OF THIRD PARTY RIGHTS. THE PROVIDER DOES NOT WARRANT THAT USE
OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR FREE. YOU ASSUME RESPONSIBILITY
FOR SELECTION OF THE SOFTWARE TO ACHIEVE ITS INTENDED RESULTS AND FOR THE
PROPER INSTALLATION, USE, AND RESULTS OBTAINED FROM THE SOFTWARE. YOU ASSUME
@@ -537,17 +575,18 @@ State of Oregon, USA.
and unless terminated. You may terminate this Agreement by destroying all
copies of the materials to which this Agreement applies. The Agreement will
terminate automatically if due to any event, including court judgment, You
-fail to perform any of its obligations hereunder. In the event of termination,
+fail to perform any of Your obligations hereunder. In the event of termination,
others that have received software from You under the terms of this Agreement
may continue to use it provided they remain in compliance with the terms of
this Agreement.
8. Your use of this Software is governed by this Lattice Semiconductor
Corporation Open Source License Agreement. However, depending on your design,
-the output files generated by the LatticeMico32 System may contain open
+the output files generated by the LatticeMico System or by any
+other Provider source code generation tool may contain open
source code provided by a third party. Specifically, the output files may
contain open source code that is licensed pursuant to the terms attached to
-the Lattice Semiconductor Corporation LatticeMico32 System License Agreement
+the Lattice Semiconductor Corporation LatticeMico System License Agreement
as Appendix B. By agreeing to the terms of this Lattice Semiconductor
Corporation Open Source License Agreement, you are also agreeing to use such
code in accordance with the terms of the agreement under which such code has
@@ -559,6 +598,10 @@ Revisions will follow the spirit of this version but will contain adjustments
and clarifications to address issues and concerns of Lattice and the user
community.
-©2006-2008 Lattice Semiconductor Corporation. You may freely distribute
+10. Any conflict between the terms of this Agreement and the licensing terms
+included in the header files provided with the Software will be resolved in
+favor of this Agreement.
+
+(c)2006-2011 Lattice Semiconductor Corporation. You may freely distribute
the text of this Agreement provided you include this copyright notice.
However, modifications to the substantive terms herein are not permitted.
View
49 boards/milkymist-one/rtl/lm32_include.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_include.v
View
2  boards/milkymist-one/rtl/system.v
@@ -899,7 +899,7 @@ sysctl #(
.csr_addr(4'h1),
.ninputs(7),
.noutputs(2),
- .systemid(32'h10004D31) /* 1.0.0 final (0) on M1 */
+ .systemid(32'h10104D31) /* 1.0.1 final (0) on M1 */
) sysctl (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
View
2  boards/milkymist-one/synthesis/common.mak
@@ -30,7 +30,7 @@ build-rescue/system-routed.ncd: build-rescue/system.ncd
cd build-rescue && par -ol high -w system.ncd system-routed.ncd
$(BUILDDIR)/system.bit: $(BUILDDIR)/system-routed.ncd
- cd $(BUILDDIR) && bitgen -g LCK_cycle:6 -g Binary:Yes -w system-routed.ncd system.bit
+ cd $(BUILDDIR) && bitgen -g LCK_cycle:6 -g Binary:Yes -g INIT_9K:Yes -w system-routed.ncd system.bit
$(BUILDDIR)/system.bin: $(BUILDDIR)/system.bit
View
2  cores/lm32/CHANGELOG
@@ -1,3 +1,5 @@
+* 2011-07-20 mwalle Upgrade to LatticeMico32 3.8
+
* 2011-03-03 lekernel Patch from Wesley W. Terpstra (GSI)
Support register file backed by ram blocks
Fix a minor problem where compilation fails when interrupts are not supported
View
49 cores/lm32/rtl/lm32_adder.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// ============================================================================/
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_adder.v
View
49 cores/lm32/rtl/lm32_addsub.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_addsub.v
View
83 cores/lm32/rtl/lm32_cpu.v
@@ -1,24 +1,50 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
+//
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_cpu.v
// Title : Top-level of CPU.
// Dependencies : lm32_include.v
//
+// Version 3.8
+// 1. Feature: Support for dynamically switching EBA to DEBA via a GPIO.
+// 2. Bug: EA now reports instruction that caused the data abort, rather than
+// next instruction.
+//
// Version 3.4
// 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were
// never serviced.
@@ -75,6 +101,11 @@ module lm32_cpu (
clk_n_i,
`endif
rst_i,
+`ifdef CFG_DEBUG_ENABLED
+ `ifdef CFG_ALTERNATE_EBA
+ at_debug,
+ `endif
+`endif
// From external devices
`ifdef CFG_INTERRUPTS_ENABLED
interrupt,
@@ -215,6 +246,12 @@ input clk_n_i; // Inverted clock
`endif
input rst_i; // Reset
+`ifdef CFG_DEBUG_ENABLED
+ `ifdef CFG_ALTERNATE_EBA
+ input at_debug; // GPIO input that maps EBA to DEBA
+ `endif
+`endif
+
`ifdef CFG_INTERRUPTS_ENABLED
input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins
`endif
@@ -543,7 +580,6 @@ reg rotate_x;
`endif
wire direction_d; // Which direction to shift in
reg direction_x;
-reg direction_m;
wire [`LM32_WORD_RNG] shifter_result_m; // Result of shifter
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
@@ -763,6 +799,11 @@ lm32_instruction_unit #(
// ----- Inputs -------
.clk_i (clk_i),
.rst_i (rst_i),
+`ifdef CFG_DEBUG_ENABLED
+ `ifdef CFG_ALTERNATE_EBA
+ .at_debug (at_debug),
+ `endif
+`endif
// From pipeline
.stall_a (stall_a),
.stall_f (stall_f),
@@ -800,7 +841,6 @@ lm32_instruction_unit #(
.i_dat_i (I_DAT_I),
.i_ack_i (I_ACK_I),
.i_err_i (I_ERR_I),
- .i_rty_i (I_RTY_I),
`endif
`ifdef CFG_HW_DEBUG_ENABLED
.jtag_read_enable (jtag_read_enable),
@@ -2352,9 +2392,6 @@ begin
exception_m <= `FALSE;
load_m <= `FALSE;
store_m <= `FALSE;
-`ifdef CFG_PL_BARREL_SHIFT_ENABLED
- direction_m <= `FALSE;
-`endif
write_enable_m <= `FALSE;
write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
condition_met_m <= `FALSE;
@@ -2478,9 +2515,6 @@ begin
`endif
end
m_bypass_enable_m <= m_bypass_enable_x;
-`ifdef CFG_PL_BARREL_SHIFT_ENABLED
- direction_m <= direction_x;
-`endif
load_m <= load_x;
store_m <= store_x;
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
@@ -2512,6 +2546,10 @@ begin
`ifdef CFG_DEBUG_ENABLED
if (exception_x == `TRUE)
if ((dc_re == `TRUE)
+`ifdef CFG_ALTERNATE_EBA
+ || (at_debug == `TRUE)
+`endif
+
|| ((debug_exception_x == `TRUE)
&& (non_debug_exception_x == `FALSE)))
branch_target_m <= {deba, eid_x, {3{1'b0}}};
@@ -2582,6 +2620,7 @@ begin
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
if ( (stall_m == `FALSE)
+ && (data_bus_error_exception == `FALSE)
&& ( (load_q_m == `TRUE)
|| (store_q_m == `TRUE)
)
View
49 cores/lm32/rtl/lm32_dcache.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_dcache.v
View
49 cores/lm32/rtl/lm32_debug.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_debug.v
View
49 cores/lm32/rtl/lm32_decoder.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_decoder.v
View
51 cores/lm32/rtl/lm32_functions.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
-//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
+//
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_functions.v
View
49 cores/lm32/rtl/lm32_icache.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_icache.v
View
80 cores/lm32/rtl/lm32_instruction_unit.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_instruction_unit.v
@@ -42,6 +63,9 @@
// : instruction cache) to lock up in to an infinite loop due to a
// : instruction bus error when EBA was set to instruction inline
// : memory.
+// Version : 3.8
+// : Feature: Support for dynamically switching EBA to DEBA via a
+// : GPIO.
// =============================================================================
`include "lm32_include.v"
@@ -54,6 +78,11 @@ module lm32_instruction_unit (
// ----- Inputs -------
clk_i,
rst_i,
+`ifdef CFG_DEBUG_ENABLED
+ `ifdef CFG_ALTERNATE_EBA
+ at_debug,
+ `endif
+`endif
// From pipeline
stall_a,
stall_f,
@@ -91,7 +120,6 @@ module lm32_instruction_unit (
i_dat_i,
i_ack_i,
i_err_i,
- i_rty_i,
`endif
`ifdef CFG_HW_DEBUG_ENABLED
jtag_read_enable,
@@ -162,6 +190,12 @@ localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
input clk_i; // Clock
input rst_i; // Reset
+`ifdef CFG_DEBUG_ENABLED
+ `ifdef CFG_ALTERNATE_EBA
+ input at_debug; // GPIO input that maps EBA to DEBA
+ `endif
+`endif
+
input stall_a; // Stall A stage instruction
input stall_f; // Stall F stage instruction
input stall_d; // Stall D stage instruction
@@ -202,7 +236,6 @@ input irom_we_xm; // Indicates if memory o
input [`LM32_WORD_RNG] i_dat_i; // Instruction Wishbone interface read data
input i_ack_i; // Instruction Wishbone interface acknowledgement
input i_err_i; // Instruction Wishbone interface error
-input i_rty_i; // Instruction Wishbone interface retry
`endif
`ifdef CFG_HW_DEBUG_ENABLED
@@ -336,6 +369,10 @@ reg bus_error_f; // Indicates if a bus er
reg jtag_access; // Indicates if a JTAG WB access is in progress
`endif
+`ifdef CFG_ALTERNATE_EBA
+reg alternate_eba_taken;
+`endif
+
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
@@ -547,7 +584,18 @@ always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
+`ifdef CFG_DEBUG_ENABLED
+ `ifdef CFG_ALTERNATE_EBA
+ if (at_debug == `TRUE)
+ pc_f <= (`CFG_DEBA_RESET-4)/4;
+ else
+ pc_f <= (`CFG_EBA_RESET-4)/4;
+ `else
+ pc_f <= (`CFG_EBA_RESET-4)/4;
+ `endif
+`else
pc_f <= (`CFG_EBA_RESET-4)/4;
+`endif
pc_d <= {`LM32_PC_WIDTH{1'b0}};
pc_x <= {`LM32_PC_WIDTH{1'b0}};
pc_m <= {`LM32_PC_WIDTH{1'b0}};
View
49 cores/lm32/rtl/lm32_interrupt.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_interrupt.v
View
49 cores/lm32/rtl/lm32_jtag.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_jtag.v
View
49 cores/lm32/rtl/lm32_load_store_unit.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_load_store_unit.v
View
49 cores/lm32/rtl/lm32_logic_op.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_logic_op.v
View
49 cores/lm32/rtl/lm32_mc_arithmetic.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm_mc_arithmetic.v
View
49 cores/lm32/rtl/lm32_multiplier.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_multiplier.v
View
49 cores/lm32/rtl/lm32_ram.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_ram.v
View
49 cores/lm32/rtl/lm32_shifter.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_shifter.v
View
65 cores/lm32/rtl/lm32_top.v
@@ -1,18 +1,39 @@
-// =============================================================================
-// COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
+// ==================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
+// ------------------------------------------------------------------
+// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
+//
+// Permission:
+//
+// Lattice Semiconductor grants permission to use this code
+// pursuant to the terms of the Lattice Semiconductor Corporation
+// Open Source License Agreement.
+//
+// Disclaimer:
+//
+// Lattice Semiconductor provides no warranty regarding the use or
+// functionality of this code. It is the user's responsibility to
+// verify the user's design for consistency and functionality through
+// the use of formal verification methods.
+//
+// --------------------------------------------------------------------
+//
+// Lattice Semiconductor Corporation
+// 5555 NE Moore Court
+// Hillsboro, OR 97214
+// U.S.A
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// 503-286-8001 (other locations)
//
-// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court 408-826-6000 (other locations)
-// Hillsboro, OR 97124 web : http://www.latticesemi.com/
-// U.S.A email: techsupport@latticesemi.com
-// =============================================================================/
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
+//
+// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_top.v
@@ -36,6 +57,11 @@ module lm32_top (
// ----- Inputs -------
clk_i,
rst_i,
+`ifdef CFG_DEBUG_ENABLED
+ `ifdef CFG_ALTERNATE_EBA
+ at_debug,
+ `endif
+`endif
// From external devices
`ifdef CFG_INTERRUPTS_ENABLED
interrupt,
@@ -98,6 +124,12 @@ module lm32_top (
input clk_i; // Clock
input rst_i; // Reset
+`ifdef CFG_DEBUG_ENABLED
+ `ifdef CFG_ALTERNATE_EBA
+ input at_debug; // GPIO input that maps EBA to DEBA
+ `endif
+`endif
+
`ifdef CFG_INTERRUPTS_ENABLED
input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins
`endif
@@ -223,6 +255,11 @@ lm32_cpu cpu (
.clk_n_i (clk_n),
`endif
.rst_i (rst_i),
+`ifdef CFG_DEBUG_ENABLED
+ `ifdef CFG_ALTERNATE_EBA
+ .at_debug (at_debug),
+ `endif
+`endif
// From external devices
`ifdef CFG_INTERRUPTS_ENABLED
.interrupt (interrupt),
View
20 software/gdbstub/crt0.S
@@ -102,7 +102,7 @@ _system_call_handler:
/* save all registers onto the stack */
save_all:
/* save origin sp */
- addi r0, r0, -144
+ addi r0, r0, -156
/* save registers */
/* 0 - R0 - saved below */
sw (r0+4), r1
@@ -142,7 +142,13 @@ save_all:
sw (r0+136), r1
rcsr r1, DEBA
sw (r0+140), r1
-
+ rcsr r1, IE
+ sw (r0+144), r1
+ rcsr r1, IM
+ sw (r0+148), r1
+ rcsr r1, IP
+ sw (r0+152), r1
+
/* work out EID from exception entry point address */
andi r1, ra, 0xff
srui r1, r1, 5
@@ -157,7 +163,7 @@ save_all:
xor r0, r0, r0
/* fix ra */
- lw r1, (sp+144)
+ lw r1, (sp+156)
sw (sp+116), r1
/* save r0 (hardcoded to 0) */
@@ -209,6 +215,10 @@ e_restore_and_return:
wcsr EBA, ea
lw ea, (sp+140)
wcsr DEBA, ea
+ lw ea, (sp+144)
+ wcsr IE, ea
+ lw ea, (sp+148)
+ wcsr IM, ea
/* restore EA from PC */
lw ea, (sp+128)
/* stack pointer must be restored last, in case it has been updated */
@@ -225,6 +235,10 @@ b_restore_and_return:
wcsr EBA, ba
lw ba, (sp+140)
wcsr DEBA, ba
+ lw ba, (sp+144)
+ wcsr IE, ba
+ lw ba, (sp+148)
+ wcsr IM, ba
/* restore BA from PC */
lw ba, (sp+128)
/* stack pointer must be restored last, in case it has been updated */
View
10 software/gdbstub/gdbstub.c
@@ -673,11 +673,13 @@ void handle_exception(unsigned int *registers)
{
int irq;
- /* make sure break is disabled.
+ /*
+ * make sure break is disabled.
* we can enter the stub with break enabled when the application calls it.
- * there is a race condition here if the break is asserted before
- * this line is executed, but the race window is small. to prevent it completely,
- * applications should disable debug exceptions before jumping to debug ROM.
+ * there is a race condition here if the break is asserted before this line
+ * is executed, but the race window is small. to prevent it completely,
+ * applications should disable debug exceptions before jumping to debug
+ * ROM.
*/
CSR_UART_BREAK = 0;
View
2  software/include/base/version.h
@@ -1,6 +1,6 @@
#ifndef __VERSION_H
#define __VERSION_H
-#define VERSION "1.0"
+#define VERSION "1.0.1"
#endif /* __VERSION_H */
View
83 tools/flterm.c
@@ -24,6 +24,7 @@
#include <sys/ioctl.h>
#include <sys/time.h>
#include <string.h>
+#include <ctype.h>
#include <termios.h>
#include <fcntl.h>
#include <unistd.h>
@@ -329,13 +330,13 @@ static void gdb_process_packet(int infd, int outfd, int altfd)
fds.revents = 0;
if(poll(&fds, 1, 100) == 0) {
/* timeout */
- if (altfd != -1) {
+ if(altfd != -1) {
write(altfd, gdbbuf, pos);
}
break;
}
- if (pos == GDBBUFLEN) {
- if (altfd != -1) {
+ if(pos == GDBBUFLEN) {
+ if(altfd != -1) {
write(altfd, gdbbuf, pos);
}
break;
@@ -344,26 +345,26 @@ static void gdb_process_packet(int infd, int outfd, int altfd)
gdbbuf[pos++] = c;
if(c == '#') {
seen_hash = 1;
- } else if (seen_hash == 0) {
+ } else if(seen_hash == 0) {
runcksum += c;
- } else if (seen_hash == 1) {
+ } else if(seen_hash == 1) {
recvcksum = hex(c) << 4;
seen_hash = 2;
- } else if (seen_hash == 2) {
+ } else if(seen_hash == 2) {
recvcksum |= hex(c);
seen_hash = 3;
}
- if (seen_hash == 3) {
+ if(seen_hash == 3) {
/* we're done */
runcksum %= 256;
- if (recvcksum == runcksum) {
- if (debug) {
+ if(recvcksum == runcksum) {
+ if(debug) {
fprintf(stderr, "[GDB %s]\n", gdbbuf);
}
write(outfd, gdbbuf, pos);
} else {
- if (altfd != -1) {
+ if(altfd != -1) {
write(altfd, gdbbuf, pos);
}
}
@@ -377,10 +378,12 @@ static void do_terminal(char *serial_port,
int doublerate, int gdb_passthrough,
const char *kernel_image, unsigned int kernel_address,
const char *cmdline, unsigned int cmdline_address,
- const char *initrd_image, unsigned int initrd_address)
+ const char *initrd_image, unsigned int initrd_address,
+ char *log_path)
{
int serialfd;
int gdbfd = -1;
+ FILE *logfd = NULL;
struct termios my_termios;
char c;
int recognized;
@@ -389,6 +392,14 @@ static void do_terminal(char *serial_port,
int rsp_pending = 0;
/* Open and configure the serial port */
+ if(log_path != NULL) {
+ logfd = fopen(log_path, "a+");
+ if(logfd == NULL) {
+ perror("Unable to open log file");
+ return;
+ }
+ }
+
serialfd = open(serial_port, O_RDWR|O_NOCTTY);
if(serialfd == -1) {
perror("Unable to open serial port");
@@ -421,7 +432,7 @@ static void do_terminal(char *serial_port,
recognized = 0;
flags = fcntl(serialfd, F_GETFL, 0);
while(1) {
- if (gdbfd == -1 && gdb_passthrough) {
+ if(gdbfd == -1 && gdb_passthrough) {
gdbfd = open("/dev/ptmx", O_RDWR);
if(grantpt(gdbfd) != 0) {
perror("grantpt()");
@@ -449,22 +460,22 @@ static void do_terminal(char *serial_port,
fcntl(serialfd, F_SETFL, flags);
if(fds[0].revents & POLLIN) {
- if (read(0, &c, 1) <= 0) break;
+ if(read(0, &c, 1) <= 0) break;
if(write(serialfd, &c, 1) <= 0) break;
}
if(fds[2].revents & POLLIN) {
rsp_pending = 1;
- if (read(gdbfd, &c, 1) <= 0) break;
- if (c == '\03') {
+ if(read(gdbfd, &c, 1) <= 0) break;
+ if(c == '\03') {
/* convert ETX to breaks */
- if (debug) {
+ if(debug) {
fprintf(stderr, "[GDB BREAK]\n");
}
tcsendbreak(serialfd, 0);
- } else if (c == '$') {
+ } else if(c == '$') {
gdb_process_packet(gdbfd, serialfd, -1);
- } else if (c == '+' || c == '-') {
+ } else if(c == '+' || c == '-') {
write(serialfd, &c, 1);
} else {
fprintf(stderr, "Internal error (line %d)", __LINE__);
@@ -481,10 +492,16 @@ static void do_terminal(char *serial_port,
if(fds[1].revents & POLLIN) {
if(read(serialfd, &c, 1) <= 0) break;
+
+ if(logfd && c && isascii(c)) {
+ fwrite(&c, sizeof(c), 1, logfd);
+ if(c == '\n') fflush(logfd);
+ }
+
if(gdbfd != -1 && rsp_pending && (c == '+' || c == '-')) {
rsp_pending = 0;
write(gdbfd, &c, 1);
- } else if (gdbfd != -1 && c == '$') {
+ } else if(gdbfd != -1 && c == '$') {
gdb_process_packet(serialfd, gdbfd, 0);
} else {
/* write to terminal */
@@ -508,9 +525,9 @@ static void do_terminal(char *serial_port,
}
close(serialfd);
- if(gdbfd != -1) {
- close(gdbfd);
- }
+
+ if(gdbfd != -1) close(gdbfd);
+ if(logfd) fclose(logfd);
}
enum {
@@ -523,7 +540,8 @@ enum {
OPTION_CMDLINE,
OPTION_CMDLINEADR,
OPTION_INITRD,
- OPTION_INITRDADR
+ OPTION_INITRDADR,
+ OPTION_LOG
};
static const struct option options[] = {
@@ -578,13 +596,18 @@ static const struct option options[] = {
.val = OPTION_INITRDADR
},
{
+ .name = "log",
+ .has_arg = 1,
+ .val = OPTION_LOG
+ },
+ {
.name = NULL
}
};
static void print_usage()
{
- fprintf(stderr, "Serial boot program for Milkymist SoC - v. 2.0\n");
+ fprintf(stderr, "Serial boot program for Milkymist SoC - v. 2.1\n");
fprintf(stderr, "Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq\n");
fprintf(stderr, "Copyright (C) 2011 Michael Walle\n");
fprintf(stderr, "Copyright (C) 2004 MontaVista Software, Inc\n\n");
@@ -597,7 +620,8 @@ static void print_usage()
fprintf(stderr, " [--double-rate] [--gdb-passthrough] [--debug]\n");
fprintf(stderr, " --kernel <kernel_image> [--kernel-adr <address>]\n");
fprintf(stderr, " [--cmdline <cmdline> [--cmdline-adr <address>]]\n");
- fprintf(stderr, " [--initrd <initrd_image> [--initrd-adr <address>]]\n\n");
+ fprintf(stderr, " [--initrd <initrd_image> [--initrd-adr <address>]]\n");
+ fprintf(stderr, " [--log <log_file>]\n\n");
printf("Default load addresses:\n");
fprintf(stderr, " kernel: 0x%08x\n", DEFAULT_KERNELADR);
fprintf(stderr, " cmdline: 0x%08x\n", DEFAULT_CMDLINEADR);
@@ -617,6 +641,7 @@ int main(int argc, char *argv[])
char *initrd_image;
unsigned int initrd_address;
char *endptr;
+ char *log_path;
struct termios otty, ntty;
/* Fetch command line arguments */
@@ -629,6 +654,7 @@ int main(int argc, char *argv[])
cmdline_address = DEFAULT_CMDLINEADR;
initrd_image = NULL;
initrd_address = DEFAULT_INITRDADR;
+ log_path = NULL;
while((opt = getopt_long(argc, argv, "", options, NULL)) != -1) {
if(opt == '?') {
print_usage();
@@ -672,6 +698,10 @@ int main(int argc, char *argv[])
initrd_address = strtoul(optarg, &endptr, 0);
if(*endptr != 0) initrd_address = 0;
break;
+ case OPTION_LOG:
+ free(log_path);
+ log_path = strdup(optarg);
+ break;
}
}
@@ -693,7 +723,8 @@ int main(int argc, char *argv[])
do_terminal(serial_port, doublerate, gdb_passthrough,
kernel_image, kernel_address,
cmdline, cmdline_address,
- initrd_image, initrd_address);
+ initrd_image, initrd_address,
+ log_path);
/* Restore stdin/out into their previous state */
tcsetattr(0, TCSANOW, &otty);

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