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2  boards/milkymist-one/rtl/lm32_include.v
@@ -148,7 +148,7 @@
148 148
 `define LM32_SHIFT_OP_LEFT              1'b1
149 149
 
150 150
 // Bus errors
151  
-//`define CFG_BUS_ERRORS_ENABLED
  151
+`define CFG_BUS_ERRORS_ENABLED
152 152
 
153 153
 // Derive macro that indicates whether we have single-stepping or not
154 154
 `ifdef CFG_ROM_DEBUG_ENABLED
24  boards/milkymist-one/rtl/system.v
@@ -760,6 +760,25 @@ assign cpu_interrupt = {16'd0,
760 760
 //---------------------------------------------------------------------------
761 761
 // LM32 CPU
762 762
 //---------------------------------------------------------------------------
  763
+wire cpuibus_err;
  764
+wire cpudbus_err;
  765
+`ifdef CFG_BUS_ERRORS_ENABLED
  766
+// Catch NULL pointers and similar errors
  767
+// NOTE: ERR is asserted at the same time as ACK, which violates
  768
+// Wishbone rule 3.45. But LM32 doesn't care.
  769
+reg locked_addr_i;
  770
+reg locked_addr_d;
  771
+always @(posedge sys_clk) begin
  772
+	locked_addr_i <= cpuibus_adr[31:18] == 14'd0;
  773
+	locked_addr_d <= cpudbus_adr[31:18] == 14'd0;
  774
+end
  775
+assign cpuibus_err = locked_addr_i & cpuibus_ack;
  776
+assign cpudbus_err = locked_addr_d & cpudbus_ack;
  777
+`else
  778
+assign cpuibus_err = 1'b0;
  779
+assign cpudbus_err = 1'b0;
  780
+`endif
  781
+
763 782
 wire ext_break;
764 783
 lm32_top cpu(
765 784
 	.clk_i(sys_clk),
@@ -786,7 +805,7 @@ lm32_top cpu(
786 805
 	.I_CTI_O(cpuibus_cti),
787 806
 	.I_LOCK_O(),
788 807
 	.I_BTE_O(),
789  
-	.I_ERR_I(1'b0),
  808
+	.I_ERR_I(cpuibus_err),
790 809
 	.I_RTY_I(1'b0),
791 810
 `ifdef CFG_EXTERNAL_BREAK_ENABLED
792 811
 	.ext_break(ext_break),
@@ -803,7 +822,7 @@ lm32_top cpu(
803 822
 	.D_CTI_O(cpudbus_cti),
804 823
 	.D_LOCK_O(),
805 824
 	.D_BTE_O(),
806  
-	.D_ERR_I(1'b0),
  825
+	.D_ERR_I(cpudbus_err),
807 826
 	.D_RTY_I(1'b0)
808 827
 );
809 828
 
@@ -1286,6 +1305,7 @@ assign phy_tx_en = 1'b0;
1286 1305
 assign phy_tx_er = 1'b0;
1287 1306
 assign phy_mii_clk = 1'b0;
1288 1307
 assign phy_mii_data = 1'bz;
  1308
+assign phy_rst_n = 1'b0;
1289 1309
 `endif
1290 1310
 
1291 1311
 always @(posedge clk50) phy_clk <= ~phy_clk;
2  cores/lm32/rtl/lm32_cpu.v
@@ -750,10 +750,8 @@ wire exception_q_w;
750 750
 `endif
751 751
 
752 752
 `ifdef CFG_DEBUG_ENABLED
753  
-`ifdef CFG_JTAG_ENABLED
754 753
 wire reset_exception;                           // Indicates if a reset exception has occured
755 754
 `endif
756  
-`endif
757 755
 `ifdef CFG_INTERRUPTS_ENABLED
758 756
 wire interrupt_exception;                       // Indicates if an interrupt exception has occured
759 757
 `endif
50  software/bios/crt0.S
@@ -38,24 +38,54 @@ _reset_handler:
38 38
 	bi	_crt0
39 39
 
40 40
 _breakpoint_handler:
41  
-	nop; nop; nop; nop
42  
-	nop; nop; nop; nop
  41
+	bi _breakpoint_handler
  42
+	nop
  43
+	nop
  44
+	nop
  45
+	nop
  46
+	nop
  47
+	nop
  48
+	nop
43 49
 
44 50
 _instruction_bus_error_handler:
45  
-	nop; nop; nop; nop
46  
-	nop; nop; nop; nop
  51
+	bi _instruction_bus_error_handler
  52
+	nop
  53
+	nop
  54
+	nop
  55
+	nop
  56
+	nop
  57
+	nop
  58
+	nop
47 59
 
48 60
 _watchpoint_hander:
49  
-	nop; nop; nop; nop
50  
-	nop; nop; nop; nop
  61
+	bi _watchpoint_hander
  62
+	nop
  63
+	nop
  64
+	nop
  65
+	nop
  66
+	nop
  67
+	nop
  68
+	nop
51 69
 
52 70
 _data_bus_error_handler:
53  
-	nop; nop; nop; nop
54  
-	nop; nop; nop; nop
  71
+	bi _data_bus_error_handler
  72
+	nop
  73
+	nop
  74
+	nop
  75
+	nop
  76
+	nop
  77
+	nop
  78
+	nop
55 79
 
56 80
 _divide_by_zero_handler:
57  
-	nop; nop; nop; nop
58  
-	nop; nop; nop; nop
  81
+	bi _divide_by_zero_handler
  82
+	nop
  83
+	nop
  84
+	nop
  85
+	nop
  86
+	nop
  87
+	nop
  88
+	nop
59 89
 
60 90
 _interrupt_handler:
61 91
 	sw      (sp+0), ra

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