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  • 3 commits
  • 4 files changed
  • 0 commit comments
  • 1 contributor
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2  boards/milkymist-one/rtl/lm32_include.v
@@ -148,7 +148,7 @@
`define LM32_SHIFT_OP_LEFT 1'b1
// Bus errors
-//`define CFG_BUS_ERRORS_ENABLED
+`define CFG_BUS_ERRORS_ENABLED
// Derive macro that indicates whether we have single-stepping or not
`ifdef CFG_ROM_DEBUG_ENABLED
View
24 boards/milkymist-one/rtl/system.v
@@ -760,6 +760,25 @@ assign cpu_interrupt = {16'd0,
//---------------------------------------------------------------------------
// LM32 CPU
//---------------------------------------------------------------------------
+wire cpuibus_err;
+wire cpudbus_err;
+`ifdef CFG_BUS_ERRORS_ENABLED
+// Catch NULL pointers and similar errors
+// NOTE: ERR is asserted at the same time as ACK, which violates
+// Wishbone rule 3.45. But LM32 doesn't care.
+reg locked_addr_i;
+reg locked_addr_d;
+always @(posedge sys_clk) begin
+ locked_addr_i <= cpuibus_adr[31:18] == 14'd0;
+ locked_addr_d <= cpudbus_adr[31:18] == 14'd0;
+end
+assign cpuibus_err = locked_addr_i & cpuibus_ack;
+assign cpudbus_err = locked_addr_d & cpudbus_ack;
+`else
+assign cpuibus_err = 1'b0;
+assign cpudbus_err = 1'b0;
+`endif
+
wire ext_break;
lm32_top cpu(
.clk_i(sys_clk),
@@ -786,7 +805,7 @@ lm32_top cpu(
.I_CTI_O(cpuibus_cti),
.I_LOCK_O(),
.I_BTE_O(),
- .I_ERR_I(1'b0),
+ .I_ERR_I(cpuibus_err),
.I_RTY_I(1'b0),
`ifdef CFG_EXTERNAL_BREAK_ENABLED
.ext_break(ext_break),
@@ -803,7 +822,7 @@ lm32_top cpu(
.D_CTI_O(cpudbus_cti),
.D_LOCK_O(),
.D_BTE_O(),
- .D_ERR_I(1'b0),
+ .D_ERR_I(cpudbus_err),
.D_RTY_I(1'b0)
);
@@ -1286,6 +1305,7 @@ assign phy_tx_en = 1'b0;
assign phy_tx_er = 1'b0;
assign phy_mii_clk = 1'b0;
assign phy_mii_data = 1'bz;
+assign phy_rst_n = 1'b0;
`endif
always @(posedge clk50) phy_clk <= ~phy_clk;
View
2  cores/lm32/rtl/lm32_cpu.v
@@ -750,10 +750,8 @@ wire exception_q_w;
`endif
`ifdef CFG_DEBUG_ENABLED
-`ifdef CFG_JTAG_ENABLED
wire reset_exception; // Indicates if a reset exception has occured
`endif
-`endif
`ifdef CFG_INTERRUPTS_ENABLED
wire interrupt_exception; // Indicates if an interrupt exception has occured
`endif
View
50 software/bios/crt0.S
@@ -38,24 +38,54 @@ _reset_handler:
bi _crt0
_breakpoint_handler:
- nop; nop; nop; nop
- nop; nop; nop; nop
+ bi _breakpoint_handler
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
_instruction_bus_error_handler:
- nop; nop; nop; nop
- nop; nop; nop; nop
+ bi _instruction_bus_error_handler
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
_watchpoint_hander:
- nop; nop; nop; nop
- nop; nop; nop; nop
+ bi _watchpoint_hander
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
_data_bus_error_handler:
- nop; nop; nop; nop
- nop; nop; nop; nop
+ bi _data_bus_error_handler
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
_divide_by_zero_handler:
- nop; nop; nop; nop
- nop; nop; nop; nop
+ bi _divide_by_zero_handler
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
_interrupt_handler:
sw (sp+0), ra

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