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MultiReg: remove idomain

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1 parent b2173bb commit 0168f83523b927bc81576fc2b16a91062310112c @sbourdeauducq sbourdeauducq committed Mar 15, 2013
Showing with 3 additions and 3 deletions.
  1. +2 −2 milkymist/dvisampler/edid.py
  2. +1 −1 milkymist/uart/__init__.py
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4 milkymist/dvisampler/edid.py
@@ -33,9 +33,9 @@ def __init__(self, default=_default_edid):
_sda_i_async = Signal()
self.sync += _sda_drv_reg.eq(sda_drv)
self.specials += [
- MultiReg(self.scl, "ext", scl_i, "sys"),
+ MultiReg(self.scl, scl_i, "sys"),
Tristate(self.sda, 0, _sda_drv_reg, _sda_i_async),
- MultiReg(_sda_i_async, "ext", sda_i, "sys")
+ MultiReg(_sda_i_async, sda_i, "sys")
]
# FIXME: understand what is really going on here and get rid of that workaround
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2 milkymist/uart/__init__.py
@@ -59,7 +59,7 @@ def __init__(self, clk_freq, baud=115200):
# RX
rx = Signal()
- self.specials += MultiReg(self.rx, "ext", rx, "sys")
+ self.specials += MultiReg(self.rx, rx, "sys")
rx_r = Signal()
rx_reg = Signal(8)
rx_bitcount = Signal(4)

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