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Send SDRAM initialization sequence and answer PHY read/write requests…

…. Obstinately refuses to work, unfortunately.
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commit 026457a98c2057dc5d6a8533cab0a8c5aea374d6 1 parent 5bc840b
Sébastien Bourdeauducq authored February 18, 2012
7  milkymist/dfii/__init__.py
@@ -83,7 +83,6 @@ def get_fragment(self):
83 83
 				phase.we_n.eq(1),
84 84
 				phase.cas_n.eq(1),
85 85
 				phase.ras_n.eq(1)
86  
-				
87 86
 			]
88 87
 		
89 88
 		# commands
@@ -101,6 +100,12 @@ def get_fragment(self):
101 100
 			)
102 101
 		]
103 102
 		
  103
+		# addresses
  104
+		comb += [
  105
+			cmdphase.address.eq(self._address.field.r),
  106
+			cmdphase.bank.eq(self._baddress.field.r)
  107
+		]
  108
+		
104 109
 		# data enables
105 110
 		sync += _data_en(self._command.re & self._rddata.r,
106 111
 			rddata_en,
75  software/bios/ddrinit.c
@@ -18,13 +18,65 @@
18 18
 #include <stdio.h>
19 19
 
20 20
 #include <hw/s6ddrphy.h>
  21
+#include <hw/dfii.h>
21 22
 
22 23
 #include "ddrinit.h"
23 24
 
  25
+static void cdelay(int i)
  26
+{
  27
+	while(i > 0) {
  28
+		__asm__ volatile("nop");
  29
+		i--;
  30
+	}
  31
+}
  32
+
  33
+static void setaddr(int a)
  34
+{
  35
+	CSR_DFII_AH = (a & 0x1fe0) >> 5;
  36
+	CSR_DFII_AL = a & 0x001f;
  37
+}
  38
+
24 39
 static void init_sequence(void)
25 40
 {
  41
+	int i;
  42
+	
26 43
 	printf("Sending initialization sequence...\n");
27  
-	// TODO
  44
+	
  45
+	/* Bring CKE high */
  46
+	setaddr(0x0000);
  47
+	CSR_DFII_BA = 0;
  48
+	CSR_DFII_CONTROL = DFII_CONTROL_CKE;
  49
+	
  50
+	/* Precharge All */
  51
+	setaddr(0x0400);
  52
+	CSR_DFII_COMMAND = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
  53
+	
  54
+	/* Load Extended Mode Register */
  55
+	CSR_DFII_BA = 1;
  56
+	setaddr(0x0000);
  57
+	CSR_DFII_COMMAND = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
  58
+	CSR_DFII_BA = 0;
  59
+	
  60
+	/* Load Mode Register */
  61
+	setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */
  62
+	CSR_DFII_COMMAND = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
  63
+	cdelay(200);
  64
+	
  65
+	/* Precharge All */
  66
+	setaddr(0x0400);
  67
+	CSR_DFII_COMMAND = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
  68
+	
  69
+	/* 2x Auto Refresh */
  70
+	for(i=0;i<2;i++) {
  71
+		setaddr(0);
  72
+		CSR_DFII_COMMAND = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS;
  73
+		cdelay(4);
  74
+	}
  75
+	
  76
+	/* Load Mode Register */
  77
+	setaddr(0x0032); /* CL=3, BL=4 */
  78
+	CSR_DFII_COMMAND = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
  79
+	cdelay(200);
28 80
 }
29 81
 
30 82
 static void calibrate_phy(void)
@@ -33,21 +85,38 @@ static void calibrate_phy(void)
33 85
 	int addr;
34 86
 	
35 87
 	printf("Calibrating PHY...\n");
  88
+	
  89
+	CSR_DFII_WRDELAY = 4;
  90
+	CSR_DFII_WRDURATION = 1;
  91
+	CSR_DFII_RDDELAY = 7;
  92
+	CSR_DFII_RDDURATION = 1;
  93
+	
  94
+	/* Use bank 0, activate row 0 */
  95
+	CSR_DFII_BA = 0;
  96
+	setaddr(0x0000);
  97
+	CSR_DFII_COMMAND = DFII_COMMAND_RAS|DFII_COMMAND_CS;
  98
+	
36 99
 	while(!(CSR_DDRPHY_STATUS & DDRPHY_STATUS_PHY_CAL_DONE)) {
  100
+		cdelay(20);
37 101
 		requests = CSR_DDRPHY_REQUESTS;
38 102
 		addr = CSR_DDRPHY_REQADDR;
39 103
 		
  104
+		setaddr(addr << 2);
40 105
 		if(requests & DDRPHY_REQUEST_READ) {
41 106
 			printf("R %d\n", addr);
42  
-			// TODO
  107
+			CSR_DFII_COMMAND = DFII_COMMAND_RDDATA|DFII_COMMAND_CAS|DFII_COMMAND_CS;
43 108
 		}
44 109
 		if(requests & DDRPHY_REQUEST_WRITE) {
45 110
 			printf("W %d\n", addr);
46  
-			// TODO
  111
+			CSR_DFII_COMMAND = DFII_COMMAND_WRDATA|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
47 112
 		}
48 113
 		
49 114
 		CSR_DDRPHY_REQUESTS = requests;
50 115
 	}
  116
+	
  117
+	/* Precharge All */
  118
+	setaddr(0x0400);
  119
+	CSR_DFII_COMMAND = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS;
51 120
 }
52 121
 
53 122
 int ddrinit(void)
2  top.py
@@ -43,7 +43,7 @@ def get():
43 43
 	# DFI
44 44
 	#
45 45
 	ddrphy0 = s6ddrphy.S6DDRPHY(1, dfi_a, dfi_ba, dfi_d)
46  
-	dfii0 = dfii.DFIInjector(2, dfi_a, dfi_ba, dfi_d, 2)
  46
+	dfii0 = dfii.DFIInjector(2, dfi_a, dfi_ba, dfi_d, 1)
47 47
 	dficon0 = dfi.Interconnect(dfii0.master, ddrphy0.dfi)
48 48
 
49 49
 	#

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