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bank/csrgen: interface -> bus

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commit 0392dd8ac2d495f2a9a11390a87668737ffc79da 1 parent bec02c4
Sébastien Bourdeauducq authored December 06, 2012

Showing 1 changed file with 7 additions and 7 deletions. Show diff stats Hide diff stats

  1. 14  top.py
14  top.py
@@ -114,13 +114,13 @@ def get():
114 114
 	fb0 = framebuffer.Framebuffer(csr_offset("FB"), asmiport_fb)
115 115
 	asmiprobe0 = asmiprobe.ASMIprobe(csr_offset("ASMIPROBE"), asmicon0.hub)
116 116
 	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
117  
-		uart0.bank.interface,
118  
-		dfii0.bank.interface,
119  
-		identifier0.bank.interface,
120  
-		timer0.bank.interface,
121  
-		minimac0.bank.interface,
122  
-		fb0.bank.interface,
123  
-		asmiprobe0.bank.interface
  117
+		uart0.bank.bus,
  118
+		dfii0.bank.bus,
  119
+		identifier0.bank.bus,
  120
+		timer0.bank.bus,
  121
+		minimac0.bank.bus,
  122
+		fb0.bank.bus,
  123
+		asmiprobe0.bank.bus
124 124
 	])
125 125
 	
126 126
 	#

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