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Fix instantiations

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commit 053f8ed82ced5a14c29a500b3f8adeaa4497bdc0 1 parent 0392dd8
@sbourdeauducq sbourdeauducq authored
Showing with 24 additions and 22 deletions.
  1. +14 −12 milkymist/framebuffer/__init__.py
  2. +10 −10 milkymist/lm32/__init__.py
View
26 milkymist/framebuffer/__init__.py
@@ -124,33 +124,35 @@ def __init__(self):
def get_fragment(self):
data_width = 2+3*_bpc_dac
+ fifo_full = Signal()
+ fifo_write_en = Signal()
+ fifo_data_out = Signal(data_width)
+ fifo_data_in = Signal(data_width)
asfifo = Instance("asfifo",
Instance.Parameter("data_width", data_width),
Instance.Parameter("address_width", 8),
- Instance.Output("data_out", data_width),
- Instance.Output("empty", 1),
+ Instance.Output("data_out", fifo_data_out),
+ Instance.Output("empty"),
Instance.Input("read_en", 1),
Instance.ClockPort("clk_read", "vga"),
- Instance.Input("data_in", data_width),
- Instance.Output("full", 1),
- Instance.Input("write_en", 1),
+ Instance.Input("data_in", fifo_data_in),
+ Instance.Output("full", fifo_full),
+ Instance.Input("write_en", fifo_write_en),
Instance.ClockPort("clk_write"),
- Instance.Input("rst", 1))
+ Instance.Input("rst", 0))
t = self.token("dac")
return Fragment(
[
- asfifo.get_io("read_en").eq(1),
Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.get_io("data_out")),
- self.endpoints["dac"].ack.eq(~asfifo.get_io("full")),
- asfifo.get_io("write_en").eq(self.endpoints["dac"].stb),
- asfifo.get_io("data_in").eq(Cat(~t.hsync, ~t.vsync, t.r, t.g, t.b)),
+ self.endpoints["dac"].ack.eq(~fifo_full),
+ fifo_write_en.eq(self.endpoints["dac"].stb),
+ fifo_data_in.eq(Cat(~t.hsync, ~t.vsync, t.r, t.g, t.b)),
- self.busy.eq(0),
- asfifo.get_io("rst").eq(0)
+ self.busy.eq(0)
],
instances=[asfifo])
View
20 milkymist/lm32/__init__.py
@@ -7,6 +7,8 @@ def __init__(self):
self.dbus = d = wishbone.Interface()
self.interrupt = Signal(32)
self.ext_break = Signal()
+ self._i_adr_o = Signal(32)
+ self._d_adr_o = Signal(32)
self._inst = Instance("lm32_top",
Instance.ClockPort("clk_i"),
Instance.ResetPort("rst_i"),
@@ -14,39 +16,37 @@ def __init__(self):
Instance.Input("interrupt", self.interrupt),
#Instance.Input("ext_break", self.ext_break),
- Instance.Output("I_ADR_O", 32),
+ Instance.Output("I_ADR_O", self._i_adr_o),
Instance.Output("I_DAT_O", i.dat_w),
Instance.Output("I_SEL_O", i.sel),
Instance.Output("I_CYC_O", i.cyc),
Instance.Output("I_STB_O", i.stb),
Instance.Output("I_WE_O", i.we),
Instance.Output("I_CTI_O", i.cti),
- Instance.Output("I_LOCK_O", 1),
+ Instance.Output("I_LOCK_O"),
Instance.Output("I_BTE_O", i.bte),
Instance.Input("I_DAT_I", i.dat_r),
Instance.Input("I_ACK_I", i.ack),
Instance.Input("I_ERR_I", i.err),
- Instance.Input("I_RTY_I", 1),
+ Instance.Input("I_RTY_I", 0),
- Instance.Output("D_ADR_O", 32),
+ Instance.Output("D_ADR_O", self._d_adr_o),
Instance.Output("D_DAT_O", d.dat_w),
Instance.Output("D_SEL_O", d.sel),
Instance.Output("D_CYC_O", d.cyc),
Instance.Output("D_STB_O", d.stb),
Instance.Output("D_WE_O", d.we),
Instance.Output("D_CTI_O", d.cti),
- Instance.Output("D_LOCK_O", 1),
+ Instance.Output("D_LOCK_O"),
Instance.Output("D_BTE_O", d.bte),
Instance.Input("D_DAT_I", d.dat_r),
Instance.Input("D_ACK_I", d.ack),
Instance.Input("D_ERR_I", d.err),
- Instance.Input("D_RTY_I", 1))
+ Instance.Input("D_RTY_I", 0))
def get_fragment(self):
comb = [
- self._inst.get_io("I_RTY_I").eq(0),
- self._inst.get_io("D_RTY_I").eq(0),
- self.ibus.adr.eq(self._inst.get_io("I_ADR_O")[2:]),
- self.dbus.adr.eq(self._inst.get_io("D_ADR_O")[2:])
+ self.ibus.adr.eq(self._i_adr_o[2:]),
+ self.dbus.adr.eq(self._d_adr_o[2:])
]
return Fragment(comb=comb, instances=[self._inst])
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