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sram: do not use MemoryPort

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commit 0620e75cb8af6de67abee43114a469955ec8fbdf 1 parent 0c29775
Sébastien Bourdeauducq authored November 26, 2012

Showing 1 changed file with 11 additions and 9 deletions. Show diff stats Hide diff stats

  1. 20  milkymist/sram/__init__.py
20  milkymist/sram/__init__.py
@@ -7,14 +7,18 @@ def __init__(self, depth):
7 7
 		self.depth = depth
8 8
 	
9 9
 	def get_fragment(self):
  10
+		# memory
  11
+		mem = Memory(32, self.depth)
  12
+		port = mem.get_port(write_capable=True, we_granularity=8)
10 13
 		# generate write enable signal
11  
-		we = Signal(BV(4))
12  
-		comb = [we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
  14
+		comb = [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
13 15
 			for i in range(4)]
14  
-		# split address
15  
-		nbits = bits_for(self.depth-1)
16  
-		partial_adr = Signal(BV(nbits))
17  
-		comb.append(partial_adr.eq(self.bus.adr[:nbits]))
  16
+		# address and data
  17
+		comb += [
  18
+			port.adr.eq(self.bus.adr[:len(port.adr)]),
  19
+			port.dat_w.eq(self.bus.dat_w),
  20
+			self.bus.dat_r.eq(port.dat_r)
  21
+		]
18 22
 		# generate ack
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 		sync = [
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 			self.bus.ack.eq(0),
@@ -22,6 +26,4 @@ def get_fragment(self):
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 				self.bus.ack.eq(1)
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 			)
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 		]
25  
-		# memory
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-		port = MemoryPort(partial_adr, self.bus.dat_r, we, self.bus.dat_w, we_granularity=8)
27  
-		return Fragment(comb, sync, memories=[Memory(32, self.depth, port)])
  29
+		return Fragment(comb, sync, memories=[mem])

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