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Get CSR base addresses from include file

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commit 141269b3842c729a90c3ff8df60396486b1f1d67 1 parent bb79817
Sébastien Bourdeauducq authored May 16, 2012

Showing 2 changed files with 20 additions and 2 deletions. Show diff stats Hide diff stats

  1. 10  cmacros.py
  2. 12  top.py
10  cmacros.py
... ...
@@ -0,0 +1,10 @@
  1
+import re
  2
+
  3
+def get_macros(filename):
  4
+	f = open(filename, "r")
  5
+	r = {}
  6
+	for line in f:
  7
+		match = re.match("\w*#define\s+(\w+)\s+(.*)", line, re.IGNORECASE)
  8
+		if match:
  9
+			r[match.group(1)] = match.group(2)
  10
+	return r
12  top.py
@@ -6,6 +6,7 @@
6 6
 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
7 7
 
8 8
 from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon
  9
+from cmacros import get_macros
9 10
 from constraints import Constraints
10 11
 
11 12
 MHz = 1000000
@@ -56,6 +57,12 @@ def ddrphy_clocking(crg, phy):
56 57
 	comb = [getattr(phy, name).eq(getattr(crg, name)) for name in names]
57 58
 	return Fragment(comb)
58 59
 
  60
+csr_macros = get_macros("common/csrbase.h")
  61
+def csr_offset(name):
  62
+	base = int(csr_macros[name + "_BASE"], 0)
  63
+	assert((base >= 0xe0000000) and (base <= 0xe0010000))
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+	return (base - 0xe0000000)//0x800
  65
+
59 66
 def get():
60 67
 	#
61 68
 	# ASMI
@@ -68,7 +75,8 @@ def get():
68 75
 	# DFI
69 76
 	#
70 77
 	ddrphy0 = s6ddrphy.S6DDRPHY(sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d)
71  
-	dfii0 = dfii.DFIInjector(1, sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d, sdram_phy.nphases)
  78
+	dfii0 = dfii.DFIInjector(csr_offset("DFII"),
  79
+		sdram_geom.mux_a, sdram_geom.bank_a, sdram_phy.dfi_d, sdram_phy.nphases)
72 80
 	dficon0 = dfi.Interconnect(dfii0.master, ddrphy0.dfi)
73 81
 	dficon1 = dfi.Interconnect(asmicon0.dfi, dfii0.slave)
74 82
 
@@ -103,7 +111,7 @@ def get():
103 111
 	#
104 112
 	# CSR
105 113
 	#
106  
-	uart0 = uart.UART(0, clk_freq, baud=115200)
  114
+	uart0 = uart.UART(csr_offset("UART"), clk_freq, baud=115200)
107 115
 	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
108 116
 		uart0.bank.interface,
109 117
 		dfii0.bank.interface

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