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framebuffer/phy: fix DVI clocking

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commit 189803416b7ecdc9e167c6ae6003b578b4b59380 1 parent e6e04a2
Sébastien Bourdeauducq authored

Showing 1 changed file with 19 additions and 12 deletions. Show diff stats Hide diff stats

  1. 31  milkymist/framebuffer/phy.py
31  milkymist/framebuffer/phy.py
... ...
@@ -1,6 +1,7 @@
1 1
 from migen.fhdl.std import *
2 2
 from migen.genlib.record import Record
3 3
 from migen.genlib.fifo import AsyncFIFO
  4
+from migen.genlib.cdc import MultiReg
4 5
 from migen.bank.description import *
5 6
 from migen.flow.actor import *
6 7
 
@@ -73,7 +74,7 @@ def __init__(self, pads_vga, pads_dvi):
73 74
 		pix_progdone = Signal()
74 75
 		pix_locked = Signal()
75 76
 		self.specials += Instance("DCM_CLKGEN",
76  
-			p_CLKFXDV_DIVIDE=2, p_CLKFX_DIVIDE=4, p_CLKFX_MD_MAX=3.0, p_CLKFX_MULTIPLY=2,
  77
+			p_CLKFXDV_DIVIDE=2, p_CLKFX_DIVIDE=4, p_CLKFX_MD_MAX=1.0, p_CLKFX_MULTIPLY=2,
77 78
 			p_CLKIN_PERIOD=20.0, p_SPREAD_SPECTRUM="NONE", p_STARTUP_WAIT="FALSE",
78 79
 		
79 80
 			i_CLKIN=ClockSignal("base50"), o_CLKFX=clk_pix_unbuffered,
@@ -148,19 +149,25 @@ def __init__(self, pads_vga, pads_dvi):
148 149
 			]
149 150
 
150 151
 		# Drive VGA/DVI clock pads
151  
-		pix_clk_io = Signal()
152  
-		self.specials += Instance("ODDR2",
153  
-			p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC",
154  
-			o_Q=pix_clk_io,
155  
-			i_C0=ClockSignal("pix"),
156  
-			i_C1=~ClockSignal("pix"),
157  
-			i_CE=1, i_D0=1, i_D1=0,
158  
-			i_R=0, i_S=0)
159 152
 		if pads_vga is not None:
160  
-			self.comb += pads_vga.clk.eq(pix_clk_io)
  153
+			self.specials += Instance("ODDR2",
  154
+				p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC",
  155
+				o_Q=pads_vga.clk,
  156
+				i_C0=ClockSignal("pix"),
  157
+				i_C1=~ClockSignal("pix"),
  158
+				i_CE=1, i_D0=1, i_D1=0,
  159
+				i_R=0, i_S=0)
161 160
 		if pads_dvi is not None:
162  
-			self.specials += Instance("OBUFDS", i_I=pix_clk_io,
163  
-				o_O=pads.clk_p, o_OB=pads.clk_n)
  161
+			dvi_clk_se = Signal()
  162
+			self.specials += Instance("ODDR2",
  163
+				p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC",
  164
+				o_Q=dvi_clk_se,
  165
+				i_C0=ClockSignal("pix"),
  166
+				i_C1=~ClockSignal("pix"),
  167
+				i_CE=1, i_D0=1, i_D1=0,
  168
+				i_R=0, i_S=0)
  169
+			self.specials += Instance("OBUFTDS", i_I=dvi_clk_se,
  170
+				o_O=pads_dvi.clk_p, o_OB=pads_dvi.clk_n)
164 171
 
165 172
 class Driver(Module, AutoCSR):
166 173
 	def __init__(self, pads_vga, pads_dvi):

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