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Remove uses of pads, new constraints system

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commit 19b1cc2529d2d09a7bf7a6b8ac5f50ac8419469a 1 parent d2c4afe
Sébastien Bourdeauducq authored April 02, 2012
129  constraints.py
... ...
@@ -1,64 +1,69 @@
1  
-def get(ns, crg0, norflash0, uart0, ddrphy0):
2  
-	constraints = []
3  
-	def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
4  
-		constraints.append((ns.get_name(signal), vec, pin, iostandard, extra))
5  
-	def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
6  
-		assert(signal.bv.width == len(pins))
7  
-		i = 0
8  
-		for p in pins:
9  
-			add(signal, p, i, iostandard, extra)
10  
-			i += 1
11  
-	
12  
-	add(crg0.clkin, "AB11", extra="TNM_NET = \"GRPclk50\"")
13  
-	add(crg0.ac97_rst_n, "D6")
14  
-	add(crg0.videoin_rst_n, "W17")
15  
-	add(crg0.flash_rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
16  
-	add(crg0.trigger_reset, "AA4")
17  
-	
18  
-	add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
19  
-		"F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20",
20  
-		"G19", "C22", "C20", "D22", "D21", "F19", "F18", "D20", "D19"],
21  
-		extra="SLEW = FAST | DRIVE = 8")
22  
-	add_vec(norflash0.d, ["AA20", "U14", "U13", "AA6", "AB6", "W4", "Y4", "Y7",
23  
-		"AA2", "AB2", "V15", "AA18", "AB18", "Y13", "AA12", "AB12"],
24  
-		extra="SLEW = FAST | DRIVE = 8 | PULLDOWN")
25  
-	add(norflash0.oe_n, "M22", extra="SLEW = FAST | DRIVE = 8")
26  
-	add(norflash0.we_n, "N20", extra="SLEW = FAST | DRIVE = 8")
27  
-	add(norflash0.ce_n, "M21", extra="SLEW = FAST | DRIVE = 8")
28  
-	
29  
-	add(uart0.tx, "L17", extra="SLEW = SLOW")
30  
-	add(uart0.rx, "K18", extra="PULLUP")
31  
-	
32  
-	ddrsettings = "IOSTANDARD = SSTL2_I"
33  
-	add(ddrphy0.sd_clk_out_p, "M3", extra=ddrsettings)
34  
-	add(ddrphy0.sd_clk_out_n, "L4", extra=ddrsettings)
35  
-	add_vec(ddrphy0.sd_a, ["B1", "B2", "H8", "J7", "E4", "D5", "K7", "F5",
36  
-		"G6", "C1", "C3", "D1", "D2"], extra=ddrsettings)
37  
-	add_vec(ddrphy0.sd_ba, ["A2", "E6"], extra=ddrsettings)
38  
-	add(ddrphy0.sd_cs_n, "F7", extra=ddrsettings)
39  
-	add(ddrphy0.sd_cke, "G7", extra=ddrsettings)
40  
-	add(ddrphy0.sd_ras_n, "E5", extra=ddrsettings)
41  
-	add(ddrphy0.sd_cas_n, "C4", extra=ddrsettings)
42  
-	add(ddrphy0.sd_we_n, "D3", extra=ddrsettings)
43  
-	add_vec(ddrphy0.sd_dq, ["Y2", "W3", "W1", "P8", "P7", "P6", "P5", "T4", "T3",
44  
-		"U4", "V3", "N6", "N7", "M7", "M8", "R4", "P4", "M6", "L6", "P3", "N4",
45  
-		"M5", "V2", "V1", "U3", "U1", "T2", "T1", "R3", "R1", "P2", "P1"],
46  
-		extra=ddrsettings)
47  
-	add_vec(ddrphy0.sd_dm, ["E1", "E3", "F3", "G4"], extra=ddrsettings)
48  
-	add_vec(ddrphy0.sd_dqs, ["F1", "F2", "H5", "H6"], extra=ddrsettings)
49  
-	
50  
-	r = ""
51  
-	for c in constraints:
52  
-		r += "NET \"" + c[0]
53  
-		if c[1] >= 0:
54  
-			r += "(" + str(c[1]) + ")"
55  
-		r += "\" LOC = " + c[2] 
56  
-		r += " | IOSTANDARD = " + c[3]
57  
-		if c[4]:
58  
-			r += " | " + c[4]
59  
-		r += ";\n"
60  
-	
61  
-	r += """
  1
+class Constraints:
  2
+	def __init__(self, crg0, norflash0, uart0, ddrphy0):
  3
+		self.constraints = []
  4
+		def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
  5
+			self.constraints.append((signal, vec, pin, iostandard, extra))
  6
+		def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
  7
+			assert(signal.bv.width == len(pins))
  8
+			i = 0
  9
+			for p in pins:
  10
+				add(signal, p, i, iostandard, extra)
  11
+				i += 1
  12
+		
  13
+		add(crg0.clkin, "AB11", extra="TNM_NET = \"GRPclk50\"")
  14
+		add(crg0.ac97_rst_n, "D6")
  15
+		add(crg0.videoin_rst_n, "W17")
  16
+		add(crg0.flash_rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
  17
+		add(crg0.trigger_reset, "AA4")
  18
+		
  19
+		add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
  20
+			"F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20",
  21
+			"G19", "C22", "C20", "D22", "D21", "F19", "F18", "D20", "D19"],
  22
+			extra="SLEW = FAST | DRIVE = 8")
  23
+		add_vec(norflash0.d, ["AA20", "U14", "U13", "AA6", "AB6", "W4", "Y4", "Y7",
  24
+			"AA2", "AB2", "V15", "AA18", "AB18", "Y13", "AA12", "AB12"],
  25
+			extra="SLEW = FAST | DRIVE = 8 | PULLDOWN")
  26
+		add(norflash0.oe_n, "M22", extra="SLEW = FAST | DRIVE = 8")
  27
+		add(norflash0.we_n, "N20", extra="SLEW = FAST | DRIVE = 8")
  28
+		add(norflash0.ce_n, "M21", extra="SLEW = FAST | DRIVE = 8")
  29
+		
  30
+		add(uart0.tx, "L17", extra="SLEW = SLOW")
  31
+		add(uart0.rx, "K18", extra="PULLUP")
  32
+		
  33
+		ddrsettings = "IOSTANDARD = SSTL2_I"
  34
+		add(ddrphy0.sd_clk_out_p, "M3", extra=ddrsettings)
  35
+		add(ddrphy0.sd_clk_out_n, "L4", extra=ddrsettings)
  36
+		add_vec(ddrphy0.sd_a, ["B1", "B2", "H8", "J7", "E4", "D5", "K7", "F5",
  37
+			"G6", "C1", "C3", "D1", "D2"], extra=ddrsettings)
  38
+		add_vec(ddrphy0.sd_ba, ["A2", "E6"], extra=ddrsettings)
  39
+		add(ddrphy0.sd_cs_n, "F7", extra=ddrsettings)
  40
+		add(ddrphy0.sd_cke, "G7", extra=ddrsettings)
  41
+		add(ddrphy0.sd_ras_n, "E5", extra=ddrsettings)
  42
+		add(ddrphy0.sd_cas_n, "C4", extra=ddrsettings)
  43
+		add(ddrphy0.sd_we_n, "D3", extra=ddrsettings)
  44
+		add_vec(ddrphy0.sd_dq, ["Y2", "W3", "W1", "P8", "P7", "P6", "P5", "T4", "T3",
  45
+			"U4", "V3", "N6", "N7", "M7", "M8", "R4", "P4", "M6", "L6", "P3", "N4",
  46
+			"M5", "V2", "V1", "U3", "U1", "T2", "T1", "R3", "R1", "P2", "P1"],
  47
+			extra=ddrsettings)
  48
+		add_vec(ddrphy0.sd_dm, ["E1", "E3", "F3", "G4"], extra=ddrsettings)
  49
+		add_vec(ddrphy0.sd_dqs, ["F1", "F2", "H5", "H6"], extra=ddrsettings)
  50
+
  51
+	def get_ios(self):
  52
+		return set([c[0] for c in self.constraints])
  53
+		
  54
+	def get_ucf(self, ns):
  55
+		r = ""
  56
+		for c in self.constraints:
  57
+			r += "NET \"" + ns.get_name(c[0])
  58
+			if c[1] >= 0:
  59
+				r += "(" + str(c[1]) + ")"
  60
+			r += "\" LOC = " + c[2] 
  61
+			r += " | IOSTANDARD = " + c[3]
  62
+			if c[4]:
  63
+				r += " | " + c[4]
  64
+			r += ";\n"
  65
+		
  66
+		r += """
62 67
 TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
63 68
 INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
64 69
 INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
@@ -66,4 +71,4 @@ def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
66 71
 PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
67 72
 """
68 73
 	
69  
-	return r
  74
+		return r
3  milkymist/m1crg/__init__.py
@@ -41,5 +41,4 @@ def __init__(self, infreq, outfreq1x):
41 41
 		)
42 42
 
43 43
 	def get_fragment(self):
44  
-		return Fragment(instances=[self._inst],
45  
-			pads={self.clkin, self.ac97_rst_n, self.videoin_rst_n, self.flash_rst_n})
  44
+		return Fragment(instances=[self._inst])
2  milkymist/norflash/__init__.py
@@ -28,4 +28,4 @@ def get_fragment(self):
28 28
 			(2*self.rd_timing + 1, [
29 29
 				self.bus.ack.eq(0)])
30 30
 		])
31  
-		return Fragment(comb, sync, pads={self.adr, self.d, self.oe_n, self.we_n, self.ce_n})
  31
+		return Fragment(comb, sync)
21  milkymist/s6ddrphy/__init__.py
@@ -7,19 +7,13 @@ def __init__(self, a, ba, d):
7 7
 		outs = []
8 8
 		inouts = []
9 9
 		
10  
-		for name in [
11  
-			"clk2x_270",
12  
-			"clk4x_wr",
13  
-			"clk4x_wr_strb",
14  
-			"clk4x_rd",
15  
-			"clk4x_rd_strb"
16  
-		]:
17  
-			s = Signal(name=name)
18  
-			setattr(self, name, s)
19  
-			ins.append((name, s))
20  
-		
21  
-		self._sd_pins = []
22 10
 		for name, width, l in [
  11
+			("clk2x_270", 1, ins),
  12
+			("clk4x_wr", 1, ins),
  13
+			("clk4x_wr_strb", 1, ins),
  14
+			("clk4x_rd", 1, ins),
  15
+			("clk4x_rd_strb", 1, ins),
  16
+			
23 17
 			("sd_clk_out_p", 1, outs),
24 18
 			("sd_clk_out_n", 1, outs),
25 19
 			("sd_a", a, outs),
@@ -37,7 +31,6 @@ def __init__(self, a, ba, d):
37 31
 			s = Signal(BV(width), name=name)
38 32
 			setattr(self, name, s)
39 33
 			l.append((name, s))
40  
-			self._sd_pins.append(s)
41 34
 		
42 35
 		self.dfi = dfi.Interface(a, ba, d, 2)
43 36
 		ins += self.dfi.get_standard_names(True, False)
@@ -55,4 +48,4 @@ def __init__(self, a, ba, d):
55 48
 			clkport="sys_clk")
56 49
 
57 50
 	def get_fragment(self):
58  
-		return Fragment(instances=[self._inst], pads=set(self._sd_pins))
  51
+		return Fragment(instances=[self._inst])
2  milkymist/uart/__init__.py
@@ -107,4 +107,4 @@ def get_fragment(self):
107 107
 		
108 108
 		return self.bank.get_fragment() \
109 109
 			+ self.events.get_fragment() \
110  
-			+ Fragment(comb, sync, pads={self.tx, self.rx})
  110
+			+ Fragment(comb, sync)
7  top.py
@@ -6,7 +6,7 @@
6 6
 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
7 7
 
8 8
 from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon
9  
-import constraints
  9
+from constraints import Constraints
10 10
 
11 11
 MHz = 1000000
12 12
 clk_freq = (83 + Fraction(1, 3))*MHz
@@ -122,11 +122,12 @@ def get():
122 122
 	crg0 = m1crg.M1CRG(50*MHz, clk_freq)
123 123
 	
124 124
 	frag = autofragment.from_local() + interrupts + ddrphy_clocking(crg0, ddrphy0)
  125
+	cst = Constraints(crg0, norflash0, uart0, ddrphy0)
125 126
 	src_verilog, vns = verilog.convert(frag,
126  
-		{crg0.trigger_reset},
  127
+		cst.get_ios(),
127 128
 		name="soc",
128 129
 		clk_signal=crg0.sys_clk,
129 130
 		rst_signal=crg0.sys_rst,
130 131
 		return_ns=True)
131  
-	src_ucf = constraints.get(vns, crg0, norflash0, uart0, ddrphy0)
  132
+	src_ucf = cst.get_ucf(vns)
132 133
 	return (src_verilog, src_ucf)

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