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dvisampler/dma: buffer full memory words

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commit 1c8ef0fe3e5a799ce811b0052a073481e26181a4 1 parent ce2f088
@sbourdeauducq sbourdeauducq authored
Showing with 23 additions and 1 deletion.
  1. +23 −1 milkymist/dvisampler/dma.py
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24 milkymist/dvisampler/dma.py
@@ -3,6 +3,7 @@
from migen.bank.description import *
from migen.bank.eventmanager import *
from migen.flow.actor import *
+from migen.genlib.fifo import SyncFIFO
from migen.actorlib import dma_lasmi
from milkymist.dvisampler.common import frame_layout
@@ -54,6 +55,27 @@ def __init__(self, nslots, addr_bits, alignment_bits):
]
self.comb += [slot.address_done.eq(self.address_done & (current_slot == n)) for n, slot in enumerate(slots)]
+class _BufferedWriter(Module):
+ def __init__(self, lasmim, depth=4):
+ self.address_data = Sink([("a", lasmim.aw), ("d", lasmim.dw)])
+ self.busy = Signal()
+
+ ###
+
+ self.submodules.writer = dma_lasmi.Writer(lasmim)
+ self.submodules.fifo = SyncFIFO(lasmim.aw + lasmim.dw, depth)
+ self.comb += [
+ self.fifo.din.eq(self.address_data.payload.raw_bits()),
+ self.fifo.we.eq(self.address_data.stb),
+ self.address_data.ack.eq(self.fifo.writable),
+
+ self.writer.address_data.payload.raw_bits().eq(self.fifo.dout),
+ self.fifo.re.eq(self.writer.address_data.ack),
+ self.writer.address_data.stb.eq(self.fifo.readable),
+
+ self.busy.eq(self.writer.busy | self.fifo.readable)
+ ]
+
class DMA(Module):
def __init__(self, lasmim, nslots):
bus_aw = lasmim.aw
@@ -112,7 +134,7 @@ def __init__(self, lasmim, nslots):
)
# bus accessor
- self.submodules._bus_accessor = dma_lasmi.Writer(lasmim)
+ self.submodules._bus_accessor = _BufferedWriter(lasmim)
self.comb += [
self._bus_accessor.address_data.payload.a.eq(current_address),
self._bus_accessor.address_data.payload.d.eq(cur_memory_word)
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