Skip to content
This repository

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
Browse code

dvisampler/dma: buffer full memory words

  • Loading branch information...
commit 1c8ef0fe3e5a799ce811b0052a073481e26181a4 1 parent ce2f088
Sébastien Bourdeauducq authored June 11, 2013

Showing 1 changed file with 23 additions and 1 deletion. Show diff stats Hide diff stats

  1. 24  milkymist/dvisampler/dma.py
24  milkymist/dvisampler/dma.py
@@ -3,6 +3,7 @@
3 3
 from migen.bank.description import *
4 4
 from migen.bank.eventmanager import *
5 5
 from migen.flow.actor import *
  6
+from migen.genlib.fifo import SyncFIFO
6 7
 from migen.actorlib import dma_lasmi
7 8
 
8 9
 from milkymist.dvisampler.common import frame_layout
@@ -54,6 +55,27 @@ def __init__(self, nslots, addr_bits, alignment_bits):
54 55
 		]
55 56
 		self.comb += [slot.address_done.eq(self.address_done & (current_slot == n)) for n, slot in enumerate(slots)]
56 57
 
  58
+class _BufferedWriter(Module):
  59
+	def __init__(self, lasmim, depth=4):
  60
+		self.address_data = Sink([("a", lasmim.aw), ("d", lasmim.dw)])
  61
+		self.busy = Signal()
  62
+
  63
+		###
  64
+
  65
+		self.submodules.writer = dma_lasmi.Writer(lasmim)
  66
+		self.submodules.fifo = SyncFIFO(lasmim.aw + lasmim.dw, depth)
  67
+		self.comb += [
  68
+			self.fifo.din.eq(self.address_data.payload.raw_bits()),
  69
+			self.fifo.we.eq(self.address_data.stb),
  70
+			self.address_data.ack.eq(self.fifo.writable),
  71
+
  72
+			self.writer.address_data.payload.raw_bits().eq(self.fifo.dout),
  73
+			self.fifo.re.eq(self.writer.address_data.ack),
  74
+			self.writer.address_data.stb.eq(self.fifo.readable),
  75
+			
  76
+			self.busy.eq(self.writer.busy | self.fifo.readable)
  77
+		]
  78
+
57 79
 class DMA(Module):
58 80
 	def __init__(self, lasmim, nslots):
59 81
 		bus_aw = lasmim.aw
@@ -112,7 +134,7 @@ def __init__(self, lasmim, nslots):
112 134
 			)
113 135
 
114 136
 		# bus accessor
115  
-		self.submodules._bus_accessor = dma_lasmi.Writer(lasmim)
  137
+		self.submodules._bus_accessor = _BufferedWriter(lasmim)
116 138
 		self.comb += [
117 139
 			self._bus_accessor.address_data.payload.a.eq(current_address),
118 140
 			self._bus_accessor.address_data.payload.d.eq(cur_memory_word)

0 notes on commit 1c8ef0f

Please sign in to comment.
Something went wrong with that request. Please try again.