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build.py: use implicit get_fragment

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1 parent a23df42 commit 1e7783a41e0a6639094967432e5c34d1ddc9e17a @sbourdeauducq sbourdeauducq committed
Showing with 1 addition and 1 deletion.
  1. +1 −1 build.py
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2 build.py
@@ -58,7 +58,7 @@ def main():
"jtag_tap_spartan6.v", "lm32_itlb.v", "lm32_dtlb.v")
plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
- plat.build_cmdline(soc.get_fragment(), clock_domains=soc.crg.get_clock_domains())
+ plat.build_cmdline(soc, clock_domains=soc.crg.get_clock_domains())
if __name__ == "__main__":
main()

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