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framebuffer/dvi: TMDS encoder test bench

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commit 20b758d52fd39db4d5bca33570ccfdd8f840f9e2 1 parent 78587d1
Sébastien Bourdeauducq authored September 17, 2013

Showing 1 changed file with 74 additions and 16 deletions. Show diff stats Hide diff stats

  1. 90  milkymist/framebuffer/dvi.py
90  milkymist/framebuffer/dvi.py
@@ -9,7 +9,7 @@ def __init__(self):
9 9
 		self.c = Signal(2)
10 10
 		self.de = Signal()
11 11
 
12  
-		self.output = Signal(10)
  12
+		self.out = Signal(10)
13 13
 
14 14
 		###
15 15
 
@@ -44,7 +44,7 @@ def __init__(self):
44 44
 		]
45 45
 
46 46
 		# stage 4 - final encoding
47  
-		cnt = Signal((5, True))
  47
+		cnt = Signal((6, True))
48 48
 
49 49
 		s_c = self.c
50 50
 		s_de = self.de
@@ -56,33 +56,91 @@ def __init__(self):
56 56
 
57 57
 		self.sync += If(s_de,
58 58
 				If((cnt == 0) | (n1q_m == n0q_m),
59  
-					self.output[9].eq(~q_m_r[8]),
60  
-					self.output[8].eq(q_m_r[8]),
  59
+					self.out[9].eq(~q_m_r[8]),
  60
+					self.out[8].eq(q_m_r[8]),
61 61
 					If(q_m_r[8],
62  
-						self.output[:8].eq(q_m_r[:8]),
  62
+						self.out[:8].eq(q_m_r[:8]),
63 63
 						cnt.eq(cnt + n1q_m - n0q_m)
64 64
 					).Else(
65  
-						self.output[:8].eq(~q_m_r[:8]),
  65
+						self.out[:8].eq(~q_m_r[:8]),
66 66
 						cnt.eq(cnt + n0q_m - n1q_m)
67 67
 					)
68 68
 				).Else(
69  
-					If((~cnt[4] & (n1q_m > n0q_m)) | (cnt[4] & (n0q_m > n1q_m)),
70  
-						self.output[9].eq(1),
71  
-						self.output[8].eq(q_m_r[8]),
72  
-						self.output[:8].eq(~q_m_r[:8]),
  69
+					If((~cnt[5] & (n1q_m > n0q_m)) | (cnt[5] & (n0q_m > n1q_m)),
  70
+						self.out[9].eq(1),
  71
+						self.out[8].eq(q_m_r[8]),
  72
+						self.out[:8].eq(~q_m_r[:8]),
73 73
 						cnt.eq(cnt + Cat(0, q_m_r[8]) + n0q_m - n1q_m)
74 74
 					).Else(
75  
-						self.output[9].eq(0),
76  
-						self.output[8].eq(q_m_r[8]),
77  
-						self.output[:8].eq(q_m_r[:8]),
  75
+						self.out[9].eq(0),
  76
+						self.out[8].eq(q_m_r[8]),
  77
+						self.out[:8].eq(q_m_r[:8]),
78 78
 						cnt.eq(cnt - Cat(0, ~q_m_r[8]) + n1q_m - n0q_m)
79 79
 					)
80 80
 				)
81 81
 			).Else(
82  
-				self.output.eq(Array(control_tokens)[s_c]),
  82
+				self.out.eq(Array(control_tokens)[s_c]),
83 83
 				cnt.eq(0)
84 84
 			)
85 85
 
  86
+class _EncoderTB(Module):
  87
+	def __init__(self, inputs):
  88
+		self.outs = []
  89
+		self._iter_inputs = iter(inputs)
  90
+		self._end_cycle = None
  91
+		self.submodules.dut = Encoder()
  92
+		self.comb += self.dut.de.eq(1)
  93
+
  94
+	def do_simulation(self, s):
  95
+		if self._end_cycle is None:
  96
+			try:
  97
+				nv = next(self._iter_inputs)
  98
+			except StopIteration:
  99
+				self._end_cycle = s.cycle_counter + 4
  100
+			else:
  101
+				s.wr(self.dut.d, nv)
  102
+		if s.cycle_counter == self._end_cycle:
  103
+			s.interrupt = True
  104
+		if s.cycle_counter > 4:
  105
+			self.outs.append(s.rd(self.dut.out))
  106
+
  107
+def _bit(i, n):
  108
+	return (i >> n) & 1
  109
+
  110
+def _decode_tmds(b):
  111
+	try:
  112
+		c = control_tokens.index(b)
  113
+		de = False
  114
+	except ValueError:
  115
+		c = 0
  116
+		de = True
  117
+	vsync = bool(c & 2)
  118
+	hsync = bool(c & 1)
  119
+
  120
+	value = _bit(b, 0) ^ _bit(b, 9)
  121
+	for i in range(1, 8):
  122
+		value |= (_bit(b, i) ^ _bit(b, i-1) ^ (~_bit(b, 8) & 1)) << i
  123
+
  124
+	return de, hsync, vsync, value
  125
+
86 126
 if __name__ == "__main__":
87  
-	from migen.fhdl import verilog
88  
-	print(verilog.convert(Encoder()))
  127
+	from migen.sim.generic import Simulator
  128
+	from random import Random
  129
+	
  130
+	rng = Random(788)
  131
+	test_list = [rng.randrange(256) for i in range(500)]
  132
+	tb = _EncoderTB(test_list)
  133
+	Simulator(tb).run()
  134
+
  135
+	check = [_decode_tmds(out)[3] for out in tb.outs]
  136
+	assert(check == test_list)
  137
+	
  138
+	nb0 = 0
  139
+	nb1 = 0
  140
+	for out in tb.outs:
  141
+		for i in range(10):
  142
+			if _bit(out, i):
  143
+				nb1 += 1
  144
+			else:
  145
+				nb0 += 1
  146
+	print("0/1: {}/{} ({:.2f})".format(nb0, nb1, nb0/nb1))

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