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dvisampler/clocking: proper pix5x reset synchronization

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commit 28cb97068c3d4a05e302f89647f42691e6663829 1 parent 5126f61
Sébastien Bourdeauducq authored March 18, 2013

Showing 1 changed file with 16 additions and 1 deletion. Show diff stats Hide diff stats

  1. 17  milkymist/dvisampler/clocking.py
17  milkymist/dvisampler/clocking.py
@@ -57,5 +57,20 @@ def __init__(self):
57 57
 		self.specials += Instance("BUFG",
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 			Instance.Input("I", pll_clk2), Instance.Output("O", self._cd_pix.clk))
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 		self.specials += MultiReg(locked_async, self.locked, "sys")
60  
-		self.specials += MultiReg(~locked_async, self._cd_pix5x.rst, "pix5x")
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 		self.comb += self._r_locked.field.w.eq(self.locked)
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+
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+		# sychronize pix5x reset
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+		# this reset is also sampled in the sys clock domain, also guarantee
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+		# a sufficient minimum pulse width.
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+		pix5x_rst_n = 1
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+		for i in range(5):
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+			new_pix5x_rst_n = Signal()
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+			self.specials += Instance("FDCE",
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+				Instance.Input("D", pix5x_rst_n),
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+				Instance.Input("CE", 1),
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+				Instance.Input("C", ClockSignal("pix5x")),
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+				Instance.Input("CLR", ~locked_async),
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+				Instance.Output("Q", new_pix5x_rst_n)
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+			)
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+			pix5x_rst_n = new_pix5x_rst_n
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+		self.comb += self._cd_pix5x.rst.eq(~pix5x_rst_n)

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