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Add on-chip SRAM

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commit 28f00c3a9adc778ddd1b7daeb29fd87ff50e4ae2 1 parent 6fde54c
Sébastien Bourdeauducq authored January 27, 2012
27  milkymist/sram/__init__.py
... ...
@@ -0,0 +1,27 @@
  1
+from migen.fhdl.structure import *
  2
+from migen.bus import wishbone
  3
+
  4
+class SRAM:
  5
+	def __init__(self, depth):
  6
+		self.bus = wishbone.Slave("sram")
  7
+		self.depth = depth
  8
+	
  9
+	def get_fragment(self):
  10
+		# generate write enable signal
  11
+		we = Signal(BV(4))
  12
+		comb = [we[i].eq(self.bus.cyc_i & self.bus.stb_i & self.bus.sel_i[3-i])
  13
+			for i in range(4)]
  14
+		# split address
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+		nbits = bits_for(self.depth-1)
  16
+		partial_adr = Signal(BV(nbits))
  17
+		comb.append(partial_adr.eq(self.bus.adr_i[:nbits]))
  18
+		# generate ack
  19
+		sync = [
  20
+			self.bus.ack_o.eq(0),
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+			If(self.bus.cyc_i & self.bus.stb_i & ~self.bus.ack_o,
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+				self.bus.ack_o.eq(1)
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+			)
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+		]
  25
+		# memory
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+		port = MemoryPort(partial_adr, self.bus.dat_o, we, self.bus.dat_i, we_granularity=8)
  27
+		return Fragment(comb, sync, memories=[Memory(32, self.depth, port)])
6  top.py
@@ -2,22 +2,24 @@
2 2
 from migen.fhdl import tools, verilog, autofragment
3 3
 from migen.bus import wishbone, csr, wishbone2csr
4 4
 
5  
-from milkymist import m1reset, clkfx, lm32, norflash, uart
  5
+from milkymist import m1reset, clkfx, lm32, norflash, uart, sram
6 6
 import constraints
7 7
 
8 8
 def get():
9 9
 	MHz = 1000000
10 10
 	clk_freq = 80*MHz
  11
+	sram_size = 4096 # in kilobytes
11 12
 	
12 13
 	clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
13 14
 	reset0 = m1reset.M1Reset()
14 15
 	
15 16
 	cpu0 = lm32.LM32()
16 17
 	norflash0 = norflash.NorFlash(25, 12)
  18
+	sram0 = sram.SRAM(sram_size//4)
17 19
 	wishbone2csr0 = wishbone2csr.WB2CSR()
18 20
 	wishbonecon0 = wishbone.InterconnectShared(
19 21
 		[cpu0.ibus, cpu0.dbus],
20  
-		[(0, norflash0.bus), (3, wishbone2csr0.wishbone)],
  22
+		[(0, norflash0.bus), (1, sram0.bus), (3, wishbone2csr0.wishbone)],
21 23
 		register=True,
22 24
 		offset=1)
23 25
 	uart0 = uart.UART(0, clk_freq, baud=115200)

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