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framebuffer: make simulation easier

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commit 2b8562492415e37d4547ec621c4c1dbbf3c71ee6 1 parent 210e473
Sébastien Bourdeauducq authored July 03, 2012
30  milkymist/framebuffer/__init__.py
@@ -2,7 +2,7 @@
2 2
 from migen.flow.actor import *
3 3
 from migen.flow.network import *
4 4
 from migen.flow import plumbing
5  
-from migen.actorlib import ala, misc, dma_asmi, structuring
  5
+from migen.actorlib import ala, misc, dma_asmi, structuring, sim
6 6
 from migen.bank.description import *
7 7
 from migen.bank import csrgen
8 8
 
@@ -202,6 +202,12 @@ def get_fragment(self):
202 202
 			],
203 203
 			instances=[asfifo])
204 204
 
  205
+def sim_fifo_gen():
  206
+	while True:
  207
+		t = sim.Token("dac")
  208
+		yield t
  209
+		print("H/V:" + str(t.value["hsync"]) + str(t.value["vsync"]))
  210
+
205 211
 class FakeDMA(Actor):
206 212
 	def __init__(self, port):
207 213
 		self.port = port
@@ -222,7 +228,7 @@ def get_fragment(self):
222 228
 		return Fragment(comb, sync)
223 229
 
224 230
 class Framebuffer:
225  
-	def __init__(self, address, asmiport):
  231
+	def __init__(self, address, asmiport, simulation=False):
226 232
 		asmi_bits = asmiport.hub.aw
227 233
 		alignment_bits = bits_for(asmiport.hub.dw//8) - 1
228 234
 		length_bits = _hbits + _vbits + 2 - alignment_bits
@@ -238,7 +244,10 @@ def __init__(self, address, asmiport):
238 244
 		cast = ActorNode(structuring.Cast(asmiport.hub.dw, packed_pixels))
239 245
 		unpack = ActorNode(structuring.Unpack(pack_factor, _pixel_layout))
240 246
 		vtg = ActorNode(VTG())
241  
-		fifo = ActorNode(FIFO())
  247
+		if simulation:
  248
+			fifo = ActorNode(sim.SimActor(sim_fifo_gen(), ("dac", Sink, _dac_layout)))
  249
+		else:
  250
+			fifo = ActorNode(FIFO())
242 251
 		
243 252
 		g = DataFlowGraph()
244 253
 		g.add_connection(fi, adrloop, source_subr=["length"])
@@ -258,17 +267,20 @@ def __init__(self, address, asmiport):
258 267
 		self.bank = csrgen.Bank(fi.actor.get_registers(), address=address)
259 268
 		
260 269
 		# VGA clock input
261  
-		self.vga_clk = fifo.actor.vga_clk
  270
+		if not simulation:
  271
+			self.vga_clk = fifo.actor.vga_clk
262 272
 		
263 273
 		# Pads
264 274
 		self.vga_psave_n = Signal()
265  
-		self.vga_hsync_n = fifo.actor.vga_hsync_n
266  
-		self.vga_vsync_n = fifo.actor.vga_vsync_n
  275
+		if not simulation:
  276
+			self.vga_hsync_n = fifo.actor.vga_hsync_n
  277
+			self.vga_vsync_n = fifo.actor.vga_vsync_n
267 278
 		self.vga_sync_n = Signal()
268 279
 		self.vga_blank_n = Signal()
269  
-		self.vga_r = fifo.actor.vga_r
270  
-		self.vga_g = fifo.actor.vga_g
271  
-		self.vga_b = fifo.actor.vga_b
  280
+		if not simulation:
  281
+			self.vga_r = fifo.actor.vga_r
  282
+			self.vga_g = fifo.actor.vga_g
  283
+			self.vga_b = fifo.actor.vga_b
272 284
 
273 285
 	def get_fragment(self):
274 286
 		comb = [
34  tb/framebuffer/framebuffer.py
... ...
@@ -0,0 +1,34 @@
  1
+from migen.fhdl.structure import *
  2
+from migen.bus import asmibus
  3
+from migen.sim.generic import Simulator, TopLevel
  4
+from migen.sim.icarus import Runner
  5
+
  6
+from milkymist.framebuffer import *
  7
+
  8
+def main():
  9
+	hub = asmibus.Hub(16, 128)
  10
+	port = hub.get_port()
  11
+	hub.finalize()
  12
+	
  13
+	dut = Framebuffer(1, port, True)
  14
+	
  15
+	fragment = hub.get_fragment() + dut.get_fragment()
  16
+	sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
  17
+	
  18
+	sim.run(1)
  19
+	def csr_w(addr, d):
  20
+		sim.wr(dut.bank.description[addr].field.storage, d)
  21
+	csr_w(1, 2) # hres
  22
+	csr_w(2, 3) # hsync_start
  23
+	csr_w(3, 4) # hsync_stop
  24
+	csr_w(4, 5) # hscan
  25
+	csr_w(5, 2) # vres
  26
+	csr_w(6, 3) # vsync_start
  27
+	csr_w(7, 4) # vsync_stop
  28
+	csr_w(8, 5) # vscan
  29
+	csr_w(10, 2*2*4) # length
  30
+	csr_w(0, 1) # enable
  31
+	
  32
+	sim.run(200)
  33
+
  34
+main()

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