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tb/asmicon_wb: better access pattern

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1 parent 87ee4ba commit 2ccdade88eef189c899a814d64b493cab2b138b2 @sbourdeauducq sbourdeauducq committed May 1, 2012
Showing with 10 additions and 1 deletion.
  1. +10 −1 tb/asmicon/asmicon_wb.py
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11 tb/asmicon/asmicon_wb.py
@@ -10,9 +10,18 @@
l2_size = 8192 # in bytes
def my_generator():
- for x in range(100):
+ for x in range(20):
+ t = TWrite(x, x)
+ yield t
+ print(str(t) + " delay=" + str(t.latency))
+ for x in range(20):
t = TRead(x)
yield t
+ print(str(t) + " delay=" + str(t.latency))
+ for x in range(20):
+ t = TRead(x+l2_size//4)
+ yield t
+ print(str(t) + " delay=" + str(t.latency))
def main():
controller = ASMIcon(sdram_phy, sdram_geom, sdram_timing)

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