Skip to content
This repository

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
Browse code

lasmicon: bandwidth monitoring

  • Loading branch information...
commit 3644d2a6effa05a52d1b77b271863003fd4c4529 1 parent 13bf6f5
Sébastien Bourdeauducq authored June 15, 2013
3  milkymist/lasmicon/__init__.py
@@ -62,3 +62,6 @@ def __init__(self, phy_settings, geom_settings, timing_settings):
62 62
 		self.submodules.multiplexer = Multiplexer(phy_settings, geom_settings, timing_settings,
63 63
 			self.bank_machines, self.refresher,
64 64
 			self.dfi, self.lasmic)
  65
+
  66
+	def get_csrs(self):
  67
+		return self.multiplexer.get_csrs()
7  milkymist/lasmicon/multiplexer.py
@@ -2,6 +2,9 @@
2 2
 from migen.genlib.roundrobin import *
3 3
 from migen.genlib.misc import optree
4 4
 from migen.genlib.fsm import FSM
  5
+from migen.bank.description import AutoCSR
  6
+
  7
+from milkymist.lasmicon.perf import Bandwidth
5 8
 
6 9
 class CommandRequest:
7 10
 	def __init__(self, a, ba):
@@ -79,7 +82,7 @@ def stb_and(cmd, attr):
79 82
 				phase.wrdata_en.eq(Array(stb_and(cmd, "is_write") for cmd in commands)[sel])
80 83
 			]
81 84
 
82  
-class Multiplexer(Module):
  85
+class Multiplexer(Module, AutoCSR):
83 86
 	def __init__(self, phy_settings, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic):
84 87
 		assert(phy_settings.nphases == len(dfi.phases))
85 88
 		if phy_settings.nphases != 2:
@@ -180,3 +183,5 @@ def anti_starvation(timeout):
180 183
 		)
181 184
 		# FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
182 185
 		self.comb += refresher.ack.eq(fsm._state == fsm.REFRESH)
  186
+
  187
+		self.submodules.bandwidth = Bandwidth(choose_req.cmd)
44  milkymist/lasmicon/perf.py
... ...
@@ -0,0 +1,44 @@
  1
+from migen.fhdl.std import *
  2
+from migen.bank.description import *
  3
+
  4
+class Bandwidth(Module, AutoCSR):
  5
+	def __init__(self, cmd, period_bits=24):
  6
+		self._r_update = CSR()
  7
+		self._r_nreads = CSRStatus(period_bits)
  8
+		self._r_nwrites = CSRStatus(period_bits)
  9
+
  10
+		###
  11
+
  12
+		cmd_stb = Signal()
  13
+		cmd_ack = Signal()
  14
+		cmd_is_read = Signal()
  15
+		cmd_is_write = Signal()
  16
+		self.sync += [
  17
+			cmd_stb.eq(cmd.stb),
  18
+			cmd_ack.eq(cmd.ack),
  19
+			cmd_is_read.eq(cmd.is_read),
  20
+			cmd_is_write.eq(cmd.is_write)
  21
+		]
  22
+
  23
+		counter = Signal(period_bits)
  24
+		period = Signal()
  25
+		nreads = Signal(period_bits)
  26
+		nwrites = Signal(period_bits)
  27
+		nreads_r = Signal(period_bits)
  28
+		nwrites_r = Signal(period_bits)
  29
+		self.sync += [
  30
+			Cat(counter, period).eq(counter + 1),
  31
+			If(period,
  32
+				nreads_r.eq(nreads),
  33
+				nwrites_r.eq(nwrites),
  34
+				nreads.eq(0),
  35
+				nwrites.eq(0)
  36
+			).Elif(cmd_stb & cmd_ack,
  37
+				If(cmd_is_read, nreads.eq(nreads + 1)),
  38
+				If(cmd_is_write, nwrites.eq(nwrites + 1)),
  39
+			),
  40
+			If(self._r_update.re,
  41
+				self._r_nreads.status.eq(nreads_r),
  42
+				self._r_nwrites.status.eq(nwrites_r)
  43
+			)
  44
+		]
19  software/videomixer/main.c
@@ -90,6 +90,24 @@ static void fb_service(void)
90 90
 	}
91 91
 }
92 92
 
  93
+static void membw_service(void)
  94
+{
  95
+	static int last_event;
  96
+	unsigned long long int nr, nw;
  97
+	unsigned long long int f;
  98
+	unsigned int rdb, wrb;
  99
+
  100
+	if(elapsed(&last_event, identifier_frequency_read())) {
  101
+		lasmicon_bandwidth_update_write(1);
  102
+		nr = lasmicon_bandwidth_nreads_read();
  103
+		nw = lasmicon_bandwidth_nwrites_read();
  104
+		f = identifier_frequency_read();
  105
+		rdb = nr*f >> (24LL - 7ULL);
  106
+		wrb = nw*f >> (24LL - 7ULL);
  107
+		printf("read: %4dMbps write: %4dMbps\n", rdb/1000000, wrb/1000000);
  108
+	}
  109
+}
  110
+
93 111
 int main(void)
94 112
 {
95 113
 	irq_setmask(0);
@@ -109,6 +127,7 @@ int main(void)
109 127
 		dvisampler1_service();
110 128
 		pots_service();
111 129
 		fb_service();
  130
+		membw_service();
112 131
 	}
113 132
 	
114 133
 	return 0;
15  top.py
@@ -75,13 +75,14 @@ class SoC(Module):
75 75
 		"timer0":				4,
76 76
 		"minimac":				5,
77 77
 		"fb":					6,
78  
-		"dvisampler0":			7,
79  
-		"dvisampler0_edid_mem":	8,
80  
-		"dvisampler1":			9,
81  
-		"dvisampler1_edid_mem":	10,
82  
-		"pots":					11,
83  
-		"buttons":				12,
84  
-		"leds":					13
  78
+		"lasmicon":				7,
  79
+		"dvisampler0":			8,
  80
+		"dvisampler0_edid_mem":	9,
  81
+		"dvisampler1":			10,
  82
+		"dvisampler1_edid_mem":	11,
  83
+		"pots":					12,
  84
+		"buttons":				13,
  85
+		"leds":					14
85 86
 	}
86 87
 
87 88
 	interrupt_map = {

0 notes on commit 3644d2a

Please sign in to comment.
Something went wrong with that request. Please try again.