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Remove ActorNode

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commit 398679062121908a9806b622d5c12a86b4dbafbf 1 parent 053f8ed
Sébastien Bourdeauducq authored December 12, 2012

Showing 1 changed file with 16 additions and 16 deletions. Show diff stats Hide diff stats

  1. 32  milkymist/framebuffer/__init__.py
32  milkymist/framebuffer/__init__.py
@@ -172,18 +172,18 @@ def __init__(self, address, asmiport, simulation=False):
172 172
 		pack_factor = asmiport.hub.dw//_bpp
173 173
 		packed_pixels = structuring.pack_layout(_pixel_layout, pack_factor)
174 174
 		
175  
-		fi = ActorNode(_FrameInitiator(asmi_bits, length_bits, alignment_bits))
176  
-		adrloop = ActorNode(misc.IntSequence(length_bits, asmi_bits))
177  
-		adrbuffer = ActorNode(plumbing.Buffer)
178  
-		dma = ActorNode(dma_asmi.Reader(asmiport))
179  
-		datbuffer = ActorNode(plumbing.Buffer)
180  
-		cast = ActorNode(structuring.Cast(asmiport.hub.dw, packed_pixels))
181  
-		unpack = ActorNode(structuring.Unpack(pack_factor, _pixel_layout))
182  
-		vtg = ActorNode(VTG())
  175
+		fi = _FrameInitiator(asmi_bits, length_bits, alignment_bits)
  176
+		adrloop = misc.IntSequence(length_bits, asmi_bits)
  177
+		adrbuffer = AbstractActor(plumbing.Buffer)
  178
+		dma = dma_asmi.Reader(asmiport)
  179
+		datbuffer = AbstractActor(plumbing.Buffer)
  180
+		cast = structuring.Cast(asmiport.hub.dw, packed_pixels)
  181
+		unpack = structuring.Unpack(pack_factor, _pixel_layout)
  182
+		vtg = VTG()
183 183
 		if simulation:
184  
-			fifo = ActorNode(sim.SimActor(sim_fifo_gen(), ("dac", Sink, _dac_layout)))
  184
+			fifo = sim.SimActor(sim_fifo_gen(), ("dac", Sink, _dac_layout))
185 185
 		else:
186  
-			fifo = ActorNode(FIFO())
  186
+			fifo = FIFO()
187 187
 		
188 188
 		g = DataFlowGraph()
189 189
 		g.add_connection(fi, adrloop, source_subr=["length", "base"])
@@ -199,20 +199,20 @@ def __init__(self, address, asmiport, simulation=False):
199 199
 		g.add_connection(vtg, fifo)
200 200
 		self._comp_actor = CompositeActor(g, debugger=False)
201 201
 		
202  
-		self.bank = csrgen.Bank(fi.actor.get_registers() + self._comp_actor.get_registers(),
  202
+		self.bank = csrgen.Bank(fi.get_registers() + self._comp_actor.get_registers(),
203 203
 			address=address)
204 204
 		
205 205
 		# Pads
206 206
 		self.vga_psave_n = Signal()
207 207
 		if not simulation:
208  
-			self.vga_hsync_n = fifo.actor.vga_hsync_n
209  
-			self.vga_vsync_n = fifo.actor.vga_vsync_n
  208
+			self.vga_hsync_n = fifo.vga_hsync_n
  209
+			self.vga_vsync_n = fifo.vga_vsync_n
210 210
 		self.vga_sync_n = Signal()
211 211
 		self.vga_blank_n = Signal()
212 212
 		if not simulation:
213  
-			self.vga_r = fifo.actor.vga_r
214  
-			self.vga_g = fifo.actor.vga_g
215  
-			self.vga_b = fifo.actor.vga_b
  213
+			self.vga_r = fifo.vga_r
  214
+			self.vga_g = fifo.vga_g
  215
+			self.vga_b = fifo.vga_b
216 216
 
217 217
 	def get_fragment(self):
218 218
 		comb = [

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