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VGA framebuffer connections

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commit 3a02524cc7cfec4290e6445973e7444d57fedc22 1 parent 59f4490
Sébastien Bourdeauducq authored June 17, 2012
1  common/csrbase.h
@@ -6,5 +6,6 @@
6 6
 #define ID_BASE		0xe0001000
7 7
 #define TIMER0_BASE	0xe0001800
8 8
 #define MINIMAC_BASE	0xe0002000
  9
+#define FB_BASE		0xe0002800
9 10
 
10 11
 #endif /* __CSRBASE_H */
10  constraints.py
... ...
@@ -1,5 +1,5 @@
1 1
 class Constraints:
2  
-	def __init__(self, crg0, norflash0, uart0, ddrphy0, minimac0):
  2
+	def __init__(self, crg0, norflash0, uart0, ddrphy0, minimac0, fb0):
3 3
 		self.constraints = []
4 4
 		def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
5 5
 			self.constraints.append((signal, vec, pin, iostandard, extra))
@@ -16,6 +16,7 @@ def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
16 16
 		add(crg0.flash_rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
17 17
 		add(crg0.trigger_reset, "AA4")
18 18
 		add(crg0.phy_clk, "M20")
  19
+		add(crg0.vga_clk_pad, "A11")
19 20
 		
20 21
 		add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
21 22
 			"F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20",
@@ -61,6 +62,13 @@ def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
61 62
 		add(minimac0.phy_col, "W20")
62 63
 		add(minimac0.phy_crs, "W22")
63 64
 		
  65
+		add_vec(fb0.vga_r, ["C6", "B6", "A6", "C7", "A7", "B8", "A8", "D9"])
  66
+		add_vec(fb0.vga_g, ["C8", "C9", "A9", "D7", "D8", "D10", "C10", "B10"])
  67
+		add_vec(fb0.vga_b, ["D11", "C12", "B12", "A12", "C13", "A13", "D14", "C14"])
  68
+		add(fb0.vga_hsync_n, "A14")
  69
+		add(fb0.vga_vsync_n, "C15")
  70
+		add(fb0.vga_psave_n, "B14")
  71
+		
64 72
 		self._phy_rx_clk = minimac0.phy_rx_clk
65 73
 		self._phy_tx_clk = minimac0.phy_tx_clk
66 74
 
19  milkymist/framebuffer/__init__.py
... ...
@@ -0,0 +1,19 @@
  1
+from migen.fhdl.structure import *
  2
+
  3
+class Framebuffer:
  4
+	def __init__(self, csr_address, asmiport):
  5
+		# VGA clock input
  6
+		self.vga_clk = Signal()
  7
+		
  8
+		# pads
  9
+		self.vga_psave_n = Signal()
  10
+		self.vga_hsync_n = Signal()
  11
+		self.vga_vsync_n = Signal()
  12
+		self.vga_sync_n = Signal()
  13
+		self.vga_blank_n = Signal()
  14
+		self.vga_r = Signal(BV(8))
  15
+		self.vga_g = Signal(BV(8))
  16
+		self.vga_b = Signal(BV(8))
  17
+
  18
+	def get_fragment(self):
  19
+		return Fragment()
4  milkymist/m1crg/__init__.py
@@ -19,7 +19,9 @@ def __init__(self, infreq, outfreq1x):
19 19
 			"clk4x_wr_strb",
20 20
 			"clk4x_rd",
21 21
 			"clk4x_rd_strb",
22  
-			"phy_clk"
  22
+			"phy_clk",
  23
+			"vga_clk",
  24
+			"vga_clk_pad"
23 25
 		]:
24 26
 			s = Signal(name=name)
25 27
 			setattr(self, name, s)
18  top.py
@@ -5,7 +5,8 @@
5 5
 from migen.fhdl import verilog, autofragment
6 6
 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
7 7
 
8  
-from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, identifier, timer, minimac3
  8
+from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon, \
  9
+	identifier, timer, minimac3, framebuffer
9 10
 from cmacros import get_macros
10 11
 from constraints import Constraints
11 12
 
@@ -75,6 +76,7 @@ def get():
75 76
 	#
76 77
 	asmicon0 = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
77 78
 	asmiport_wb = asmicon0.hub.get_port()
  79
+	asmiport_fb = asmicon0.hub.get_port()
78 80
 	asmicon0.finalize()
79 81
 	
80 82
 	#
@@ -122,12 +124,14 @@ def get():
122 124
 	uart0 = uart.UART(csr_offset("UART"), clk_freq, baud=115200)
123 125
 	identifier0 = identifier.Identifier(csr_offset("ID"), 0x4D31, version, int(clk_freq))
124 126
 	timer0 = timer.Timer(csr_offset("TIMER0"))
  127
+	fb0 = framebuffer.Framebuffer(csr_offset("FB"), asmiport_fb)
125 128
 	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
126 129
 		uart0.bank.interface,
127 130
 		dfii0.bank.interface,
128 131
 		identifier0.bank.interface,
129 132
 		timer0.bank.interface,
130  
-		minimac0.bank.interface
  133
+		minimac0.bank.interface,
  134
+		#fb0.bank.interface
131 135
 	])
132 136
 	
133 137
 	#
@@ -144,8 +148,14 @@ def get():
144 148
 	#
145 149
 	crg0 = m1crg.M1CRG(50*MHz, clk_freq)
146 150
 	
147  
-	frag = autofragment.from_local() + interrupts + ddrphy_clocking(crg0, ddrphy0)
148  
-	cst = Constraints(crg0, norflash0, uart0, ddrphy0, minimac0)
  151
+	vga_clocking = Fragment([
  152
+		fb0.vga_clk.eq(crg0.vga_clk)
  153
+	])
  154
+	frag = autofragment.from_local() \
  155
+		+ interrupts \
  156
+		+ ddrphy_clocking(crg0, ddrphy0) \
  157
+		+ vga_clocking
  158
+	cst = Constraints(crg0, norflash0, uart0, ddrphy0, minimac0, fb0)
149 159
 	src_verilog, vns = verilog.convert(frag,
150 160
 		cst.get_ios(),
151 161
 		name="soc",
46  verilog/m1crg/m1crg.v
@@ -23,7 +23,11 @@ module m1crg #(
23 23
 	output clk4x_rd_strb,
24 24
 	
25 25
 	/* Ethernet PHY clock */
26  
-	output reg phy_clk
  26
+	output reg phy_clk,	/* < unbuffered, to I/O */
  27
+	
  28
+	/* VGA clock */
  29
+	output vga_clk,		/* < buffered, to internal clock network */
  30
+	output vga_clk_pad	/* < forwarded through ODDR2, to I/O */
27 31
 );
28 32
 
29 33
 /*
@@ -190,5 +194,45 @@ BUFG bufg_x1(
190 194
 /* Ethernet PHY */
191 195
 always @(posedge pllout4)
192 196
 	phy_clk <= ~phy_clk;
  197
+
  198
+/* VGA clock */
  199
+// TODO: hook up the reprogramming interface
  200
+DCM_CLKGEN #(
  201
+	.CLKFXDV_DIVIDE(2),
  202
+	.CLKFX_DIVIDE(4),
  203
+	.CLKFX_MD_MAX(2.0),
  204
+	.CLKFX_MULTIPLY(2),
  205
+	.CLKIN_PERIOD(0.0),
  206
+	.SPREAD_SPECTRUM("NONE"),
  207
+	.STARTUP_WAIT("FALSE")
  208
+) vga_clock_gen (
  209
+	.CLKFX(vga_clk),
  210
+	.CLKFX180(),
  211
+	.CLKFXDV(),
  212
+	.LOCKED(),
  213
+	.PROGDONE(),
  214
+	.STATUS(),
  215
+	.CLKIN(pllout4),
  216
+	.FREEZEDCM(1'b0),
  217
+	.PROGCLK(1'b0),
  218
+	.PROGDATA(),
  219
+	.PROGEN(1'b0),
  220
+	.RST(1'b0)
  221
+);
  222
+
  223
+ODDR2 #(
  224
+	.DDR_ALIGNMENT("NONE"),
  225
+	.INIT(1'b0),
  226
+	.SRTYPE("SYNC")
  227
+) vga_clock_forward (
  228
+	.Q(vga_clk_pad),
  229
+	.C0(vga_clk),
  230
+	.C1(~vga_clk),
  231
+	.CE(1'b1),
  232
+	.D0(1'b1),
  233
+	.D1(1'b0),
  234
+	.R(1'b0),
  235
+	.S(1'b0)
  236
+);
193 237
  
194 238
 endmodule

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