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framebuffer: reorganize in preparation for mixer

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commit 3ab83fb693e4e5595e518b3e3ba4f79797bcad45 1 parent 6f11ddb
Sébastien Bourdeauducq authored
172  milkymist/framebuffer/__init__.py
... ...
@@ -1,183 +1,23 @@
1 1
 from migen.fhdl.structure import *
2  
-from migen.fhdl.specials import Instance
3 2
 from migen.fhdl.module import Module
4  
-from migen.genlib.record import Record
5  
-from migen.genlib.fifo import AsyncFIFO
6  
-from migen.flow.actor import *
7 3
 from migen.flow.network import *
8  
-from migen.flow.transactions import *
9 4
 from migen.bank.description import CSRStorage
10 5
 from migen.actorlib import dma_asmi, structuring, sim, spi
11 6
 
12  
-_hbits = 11
13  
-_vbits = 12
14  
-
15  
-_bpp = 32
16  
-_bpc = 10
17  
-_pixel_layout_s = [
18  
-	("pad", _bpp-3*_bpc),
19  
-	("r", _bpc),
20  
-	("g", _bpc),
21  
-	("b", _bpc)
22  
-]
23  
-_pixel_layout = [
24  
-	("p0", _pixel_layout_s),
25  
-	("p1", _pixel_layout_s)
26  
-]
27  
-
28  
-_bpc_dac = 8
29  
-_dac_layout_s = [
30  
-	("r", _bpc_dac),
31  
-	("g", _bpc_dac),
32  
-	("b", _bpc_dac)
33  
-]
34  
-_dac_layout = [
35  
-	("hsync", 1),
36  
-	("vsync", 1),
37  
-	("p0", _dac_layout_s),
38  
-	("p1", _dac_layout_s)
39  
-]
40  
-
41  
-class _FrameInitiator(spi.SingleGenerator):
42  
-	def __init__(self):
43  
-		layout = [
44  
-			("hres", _hbits, 640, 1),
45  
-			("hsync_start", _hbits, 656, 1),
46  
-			("hsync_end", _hbits, 752, 1),
47  
-			("hscan", _hbits, 800, 1),
48  
-			
49  
-			("vres", _vbits, 480),
50  
-			("vsync_start", _vbits, 492),
51  
-			("vsync_end", _vbits, 494),
52  
-			("vscan", _vbits, 525)
53  
-		]
54  
-		spi.SingleGenerator.__init__(self, layout, spi.MODE_EXTERNAL)
55  
-
56  
-class VTG(Module):
57  
-	def __init__(self):
58  
-		self.timing = Sink([
59  
-				("hres", _hbits),
60  
-				("hsync_start", _hbits),
61  
-				("hsync_end", _hbits),
62  
-				("hscan", _hbits),
63  
-				("vres", _vbits),
64  
-				("vsync_start", _vbits),
65  
-				("vsync_end", _vbits),
66  
-				("vscan", _vbits)])
67  
-		self.pixels = Sink(_pixel_layout)
68  
-		self.dac = Source(_dac_layout)
69  
-		self.busy = Signal()
70  
-
71  
-		hactive = Signal()
72  
-		vactive = Signal()
73  
-		active = Signal()
74  
-		
75  
-		generate_en = Signal()
76  
-		hcounter = Signal(_hbits)
77  
-		vcounter = Signal(_vbits)
78  
-		
79  
-		skip = _bpc - _bpc_dac
80  
-		self.comb += [
81  
-			active.eq(hactive & vactive),
82  
-			If(active,
83  
-				[getattr(getattr(self.dac.payload, p), c).eq(getattr(getattr(self.pixels.payload, p), c)[skip:])
84  
-					for p in ["p0", "p1"] for c in ["r", "g", "b"]]
85  
-			),
86  
-			
87  
-			generate_en.eq(self.timing.stb & (~active | self.pixels.stb)),
88  
-			self.pixels.ack.eq(self.dac.ack & active),
89  
-			self.dac.stb.eq(generate_en),
90  
-			self.busy.eq(generate_en)
91  
-		]
92  
-		tp = self.timing.payload
93  
-		self.sync += [
94  
-			self.timing.ack.eq(0),
95  
-			If(generate_en & self.dac.ack,
96  
-				hcounter.eq(hcounter + 1),
97  
-			
98  
-				If(hcounter == 0, hactive.eq(1)),
99  
-				If(hcounter == tp.hres, hactive.eq(0)),
100  
-				If(hcounter == tp.hsync_start, self.dac.payload.hsync.eq(1)),
101  
-				If(hcounter == tp.hsync_end, self.dac.payload.hsync.eq(0)),
102  
-				If(hcounter == tp.hscan,
103  
-					hcounter.eq(0),
104  
-					If(vcounter == tp.vscan,
105  
-						vcounter.eq(0),
106  
-						self.timing.ack.eq(1)
107  
-					).Else(
108  
-						vcounter.eq(vcounter + 1)
109  
-					)
110  
-				),
111  
-				
112  
-				If(vcounter == 0, vactive.eq(1)),
113  
-				If(vcounter == tp.vres, vactive.eq(0)),
114  
-				If(vcounter == tp.vsync_start, self.dac.payload.vsync.eq(1)),
115  
-				If(vcounter == tp.vsync_end, self.dac.payload.vsync.eq(0))
116  
-			)
117  
-		]
118  
-
119  
-class FIFO(Module):
120  
-	def __init__(self):
121  
-		self.dac = Sink(_dac_layout)
122  
-		self.busy = Signal()
123  
-		
124  
-		self.vga_hsync_n = Signal()
125  
-		self.vga_vsync_n = Signal()
126  
-		self.vga_r = Signal(_bpc_dac)
127  
-		self.vga_g = Signal(_bpc_dac)
128  
-		self.vga_b = Signal(_bpc_dac)
129  
-	
130  
-		###
131  
-
132  
-		data_width = 2+2*3*_bpc_dac
133  
-		fifo = AsyncFIFO(data_width, 256)
134  
-		self.add_submodule(fifo, {"write": "sys", "read": "vga"})
135  
-		fifo_in = self.dac.payload
136  
-		fifo_out = Record(_dac_layout)
137  
-		self.comb += [
138  
-			self.dac.ack.eq(fifo.writable),
139  
-			fifo.we.eq(self.dac.stb),
140  
-			fifo.din.eq(fifo_in.raw_bits()),
141  
-			fifo_out.raw_bits().eq(fifo.dout),
142  
-			self.busy.eq(0)
143  
-		]
144  
-
145  
-		pix_parity = Signal()
146  
-		self.sync.vga += [
147  
-			pix_parity.eq(~pix_parity),
148  
-			self.vga_hsync_n.eq(~fifo_out.hsync),
149  
-			self.vga_vsync_n.eq(~fifo_out.vsync),
150  
-			If(pix_parity,
151  
-				self.vga_r.eq(fifo_out.p1.r),
152  
-				self.vga_g.eq(fifo_out.p1.g),
153  
-				self.vga_b.eq(fifo_out.p1.b)
154  
-			).Else(
155  
-				self.vga_r.eq(fifo_out.p0.r),
156  
-				self.vga_g.eq(fifo_out.p0.g),
157  
-				self.vga_b.eq(fifo_out.p0.b)
158  
-			)
159  
-		]
160  
-		self.comb += fifo.re.eq(pix_parity)
161  
-
162  
-def sim_fifo_gen():
163  
-	while True:
164  
-		t = Token("dac")
165  
-		yield t
166  
-		print("H/V:" + str(t.value["hsync"]) + str(t.value["vsync"])
167  
-			+ " " + str(t.value["r"]) + " " + str(t.value["g"]) + " " + str(t.value["b"]))
  7
+from milkymist.framebuffer.lib import bpp, pixel_layout, dac_layout, FrameInitiator, VTG, FIFO
168 8
 
169 9
 class Framebuffer(Module):
170 10
 	def __init__(self, pads, asmiport, simulation=False):
171  
-		pack_factor = asmiport.hub.dw//(2*_bpp)
172  
-		packed_pixels = structuring.pack_layout(_pixel_layout, pack_factor)
  11
+		pack_factor = asmiport.hub.dw//(2*bpp)
  12
+		packed_pixels = structuring.pack_layout(pixel_layout, pack_factor)
173 13
 		
174  
-		fi = _FrameInitiator()
  14
+		fi = FrameInitiator()
175 15
 		dma = spi.DMAReadController(dma_asmi.Reader(asmiport), spi.MODE_EXTERNAL, length_reset=640*480*4)
176 16
 		cast = structuring.Cast(asmiport.hub.dw, packed_pixels, reverse_to=True)
177  
-		unpack = structuring.Unpack(pack_factor, _pixel_layout)
  17
+		unpack = structuring.Unpack(pack_factor, pixel_layout)
178 18
 		vtg = VTG()
179 19
 		if simulation:
180  
-			fifo = sim.SimActor(sim_fifo_gen(), ("dac", Sink, _dac_layout))
  20
+			fifo = sim.SimActor(sim_fifo_gen(), ("dac", Sink, dac_layout))
181 21
 		else:
182 22
 			fifo = FIFO()
183 23
 		
167  milkymist/framebuffer/lib.py
... ...
@@ -0,0 +1,167 @@
  1
+from migen.fhdl.structure import *
  2
+from migen.fhdl.module import Module
  3
+from migen.genlib.record import Record
  4
+from migen.genlib.fifo import AsyncFIFO
  5
+from migen.flow.actor import *
  6
+from migen.flow.network import *
  7
+from migen.flow.transactions import *
  8
+from migen.bank.description import CSRStorage
  9
+from migen.actorlib import spi
  10
+
  11
+_hbits = 11
  12
+_vbits = 12
  13
+
  14
+bpp = 32
  15
+bpc = 10
  16
+pixel_layout_s = [
  17
+	("pad", bpp-3*bpc),
  18
+	("r", bpc),
  19
+	("g", bpc),
  20
+	("b", bpc)
  21
+]
  22
+pixel_layout = [
  23
+	("p0", pixel_layout_s),
  24
+	("p1", pixel_layout_s)
  25
+]
  26
+
  27
+bpc_dac = 8
  28
+dac_layout_s = [
  29
+	("r", bpc_dac),
  30
+	("g", bpc_dac),
  31
+	("b", bpc_dac)
  32
+]
  33
+dac_layout = [
  34
+	("hsync", 1),
  35
+	("vsync", 1),
  36
+	("p0", dac_layout_s),
  37
+	("p1", dac_layout_s)
  38
+]
  39
+
  40
+class FrameInitiator(spi.SingleGenerator):
  41
+	def __init__(self):
  42
+		layout = [
  43
+			("hres", _hbits, 640, 1),
  44
+			("hsync_start", _hbits, 656, 1),
  45
+			("hsync_end", _hbits, 752, 1),
  46
+			("hscan", _hbits, 800, 1),
  47
+			
  48
+			("vres", _vbits, 480),
  49
+			("vsync_start", _vbits, 492),
  50
+			("vsync_end", _vbits, 494),
  51
+			("vscan", _vbits, 525)
  52
+		]
  53
+		spi.SingleGenerator.__init__(self, layout, spi.MODE_EXTERNAL)
  54
+
  55
+class VTG(Module):
  56
+	def __init__(self):
  57
+		self.timing = Sink([
  58
+				("hres", _hbits),
  59
+				("hsync_start", _hbits),
  60
+				("hsync_end", _hbits),
  61
+				("hscan", _hbits),
  62
+				("vres", _vbits),
  63
+				("vsync_start", _vbits),
  64
+				("vsync_end", _vbits),
  65
+				("vscan", _vbits)])
  66
+		self.pixels = Sink(pixel_layout)
  67
+		self.dac = Source(dac_layout)
  68
+		self.busy = Signal()
  69
+
  70
+		hactive = Signal()
  71
+		vactive = Signal()
  72
+		active = Signal()
  73
+		
  74
+		generate_en = Signal()
  75
+		hcounter = Signal(_hbits)
  76
+		vcounter = Signal(_vbits)
  77
+		
  78
+		skip = bpc - bpc_dac
  79
+		self.comb += [
  80
+			active.eq(hactive & vactive),
  81
+			If(active,
  82
+				[getattr(getattr(self.dac.payload, p), c).eq(getattr(getattr(self.pixels.payload, p), c)[skip:])
  83
+					for p in ["p0", "p1"] for c in ["r", "g", "b"]]
  84
+			),
  85
+			
  86
+			generate_en.eq(self.timing.stb & (~active | self.pixels.stb)),
  87
+			self.pixels.ack.eq(self.dac.ack & active),
  88
+			self.dac.stb.eq(generate_en),
  89
+			self.busy.eq(generate_en)
  90
+		]
  91
+		tp = self.timing.payload
  92
+		self.sync += [
  93
+			self.timing.ack.eq(0),
  94
+			If(generate_en & self.dac.ack,
  95
+				hcounter.eq(hcounter + 1),
  96
+			
  97
+				If(hcounter == 0, hactive.eq(1)),
  98
+				If(hcounter == tp.hres, hactive.eq(0)),
  99
+				If(hcounter == tp.hsync_start, self.dac.payload.hsync.eq(1)),
  100
+				If(hcounter == tp.hsync_end, self.dac.payload.hsync.eq(0)),
  101
+				If(hcounter == tp.hscan,
  102
+					hcounter.eq(0),
  103
+					If(vcounter == tp.vscan,
  104
+						vcounter.eq(0),
  105
+						self.timing.ack.eq(1)
  106
+					).Else(
  107
+						vcounter.eq(vcounter + 1)
  108
+					)
  109
+				),
  110
+				
  111
+				If(vcounter == 0, vactive.eq(1)),
  112
+				If(vcounter == tp.vres, vactive.eq(0)),
  113
+				If(vcounter == tp.vsync_start, self.dac.payload.vsync.eq(1)),
  114
+				If(vcounter == tp.vsync_end, self.dac.payload.vsync.eq(0))
  115
+			)
  116
+		]
  117
+
  118
+class FIFO(Module):
  119
+	def __init__(self):
  120
+		self.dac = Sink(dac_layout)
  121
+		self.busy = Signal()
  122
+		
  123
+		self.vga_hsync_n = Signal()
  124
+		self.vga_vsync_n = Signal()
  125
+		self.vga_r = Signal(bpc_dac)
  126
+		self.vga_g = Signal(bpc_dac)
  127
+		self.vga_b = Signal(bpc_dac)
  128
+	
  129
+		###
  130
+
  131
+		data_width = 2+2*3*bpc_dac
  132
+		fifo = AsyncFIFO(data_width, 256)
  133
+		self.add_submodule(fifo, {"write": "sys", "read": "vga"})
  134
+		fifo_in = self.dac.payload
  135
+		fifo_out = Record(dac_layout)
  136
+		self.comb += [
  137
+			self.dac.ack.eq(fifo.writable),
  138
+			fifo.we.eq(self.dac.stb),
  139
+			fifo.din.eq(fifo_in.raw_bits()),
  140
+			fifo_out.raw_bits().eq(fifo.dout),
  141
+			self.busy.eq(0)
  142
+		]
  143
+
  144
+		pix_parity = Signal()
  145
+		self.sync.vga += [
  146
+			pix_parity.eq(~pix_parity),
  147
+			self.vga_hsync_n.eq(~fifo_out.hsync),
  148
+			self.vga_vsync_n.eq(~fifo_out.vsync),
  149
+			If(pix_parity,
  150
+				# FIXME: p0/p1 should be the other way around. Clarify this.
  151
+				self.vga_r.eq(fifo_out.p0.r),
  152
+				self.vga_g.eq(fifo_out.p0.g),
  153
+				self.vga_b.eq(fifo_out.p0.b)
  154
+			).Else(
  155
+				self.vga_r.eq(fifo_out.p1.r),
  156
+				self.vga_g.eq(fifo_out.p1.g),
  157
+				self.vga_b.eq(fifo_out.p1.b)
  158
+			)
  159
+		]
  160
+		self.comb += fifo.re.eq(pix_parity)
  161
+
  162
+def sim_fifo_gen():
  163
+	while True:
  164
+		t = Token("dac")
  165
+		yield t
  166
+		print("H/V:" + str(t.value["hsync"]) + str(t.value["vsync"])
  167
+			+ " " + str(t.value["r"]) + " " + str(t.value["g"]) + " " + str(t.value["b"]))

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