Skip to content
This repository

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
Browse code

Use new syntax

  • Loading branch information...
commit 3b640c45bb1cfe61f339378dab69c16b2f8e7364 1 parent 6664af7
Sébastien Bourdeauducq authored December 18, 2011
4  milkymist/clkfx/__init__.py
@@ -4,8 +4,8 @@
4 4
 
5 5
 class Inst:
6 6
 	def __init__(self, infreq, outfreq):
7  
-		declare_signal(self, "clkin")
8  
-		declare_signal(self, "clkout")
  7
+		self.clkin = Signal()
  8
+		self.clkout = Signal()
9 9
 		
10 10
 		ratio = Fraction(outfreq)/Fraction(infreq)
11 11
 		appr = ratio.limit_denominator(32)
4  milkymist/lm32/__init__.py
@@ -5,8 +5,8 @@ class Inst:
5 5
 	def __init__(self):
6 6
 		self.ibus = i = wishbone.Master("lm32i")
7 7
 		self.dbus = d = wishbone.Master("lm32d")
8  
-		declare_signal(self, "interrupt", BV(32))
9  
-		declare_signal(self, "ext_break")
  8
+		self.interrupt = Signal(BV(32))
  9
+		self.ext_break = Signal()
10 10
 		self._inst = Instance("lm32_top",
11 11
 			[("I_ADR_O", i.adr_o),
12 12
 			("I_DAT_O", i.dat_o),
13  milkymist/m1reset/__init__.py
... ...
@@ -1,15 +1,12 @@
1  
-from functools import partial
2  
-
3 1
 from migen.fhdl.structure import *
4 2
 
5 3
 class Inst:
6 4
 	def __init__(self):
7  
-		d = partial(declare_signal, self)
8  
-		d("trigger_reset")
9  
-		d("sys_rst")
10  
-		d("ac97_rst_n")
11  
-		d("videoin_rst_n")
12  
-		d("flash_rst_n")
  5
+		self.trigger_reset = Signal()
  6
+		self.sys_rst = Signal()
  7
+		self.ac97_rst_n = Signal()
  8
+		self.videoin_rst_n = Signal()
  9
+		self.flash_rst_n = Signal()
13 10
 		self._inst = Instance("m1reset",
14 11
 			[("sys_rst", self.sys_rst),
15 12
 			("ac97_rst_n", self.ac97_rst_n),
13  milkymist/norflash/__init__.py
... ...
@@ -1,5 +1,3 @@
1  
-from functools import partial
2  
-
3 1
 from migen.fhdl.structure import *
4 2
 from migen.bus import wishbone
5 3
 from migen.corelogic import timeline
@@ -7,12 +5,11 @@
7 5
 class Inst:
8 6
 	def __init__(self, adr_width, rd_timing):
9 7
 		self.bus = wishbone.Slave("norflash")
10  
-		d = partial(declare_signal, self)
11  
-		d("adr", BV(adr_width-1))
12  
-		d("d", BV(16))
13  
-		d("oe_n")
14  
-		d("we_n")
15  
-		d("ce_n")
  8
+		self.adr = Signal(BV(adr_width-1))
  9
+		self.d = Signal(BV(16))
  10
+		self.oe_n = Signal()
  11
+		self.we_n = Signal()
  12
+		self.ce_n = Signal()
16 13
 		self.timeline = timeline.Inst(self.bus.cyc_i & self.bus.stb_i,
17 14
 			[(0, [self.adr.eq(Cat(0, self.bus.adr_i[2:adr_width]))]),
18 15
 			(rd_timing, [
76  milkymist/uart/__init__.py
... ...
@@ -1,5 +1,3 @@
1  
-from functools import partial
2  
-
3 1
 from migen.fhdl.structure import *
4 2
 from migen.bank.description import *
5 3
 from migen.bank import csrgen
@@ -13,44 +11,54 @@ def __init__(self, address, clk_freq, baud=115200):
13 11
 		self._f_thre = Field(stat, "thre", access_bus=READ_ONLY, access_dev=WRITE_ONLY)
14 12
 		
15 13
 		self.bank = csrgen.Bank([rxtx, divisor, stat], address=address)
16  
-		d = partial(declare_signal, self)
17  
-		d("tx", reset=1)
18  
-		d("rx")
  14
+		self.tx = Signal(reset=1)
  15
+		self.rx = Signal()
19 16
 		
20  
-		d("_enable16")
21  
-		d("_enable16_counter", BV(16))
22  
-		d("_tx_reg", BV(8))
23  
-		d("_tx_bitcount", BV(4))
24  
-		d("_tx_count16", BV(4))
25  
-		d("_tx_busy")
26 17
 		self.divisor = int(clk_freq/baud/16); # TODO
27 18
 	
28 19
 	def get_fragment(self):
29  
-		comb = [self._enable16.eq(self._enable16_counter == Constant(0, BV(16)))]
30  
-		sync = [self._enable16_counter.eq(self._enable16_counter - 1),
31  
-			If(self._enable16, self._enable16_counter.eq(self.divisor - 1))] # TODO
  20
+		enable16 = Signal()
  21
+		enable16_counter = Signal(BV(16))
  22
+		comb = [
  23
+			enable16.eq(enable16_counter == Constant(0, BV(16)))
  24
+		]
  25
+		sync = [
  26
+			enable16_counter.eq(enable16_counter - 1),
  27
+			If(enable16,
  28
+				enable16_counter.eq(self.divisor - 1)) # TODO
  29
+		]
32 30
 		
33  
-		sync += [If(self._rxtx.dev_re,
34  
-			self._tx_reg.eq(self._rxtx.dev_r),
35  
-			self._tx_bitcount.eq(0),
36  
-			self._tx_count16.eq(1),
37  
-			self._tx_busy.eq(1),
38  
-			self.tx.eq(0)
39  
-		).Elif(self._enable16 & self._tx_busy,
40  
-			self._tx_count16.eq(self._tx_count16 + 1),
41  
-			If(self._tx_count16 == Constant(0, BV(4)),
42  
-				self._tx_bitcount.eq(self._tx_bitcount + 1),
43  
-				If(self._tx_bitcount == 8,
44  
-					self.tx.eq(1)
45  
-				).Elif(self._tx_bitcount == 9,
46  
-					self.tx.eq(1),
47  
-					self._tx_busy.eq(0)
48  
-				).Else(
49  
-					self.tx.eq(self._tx_reg[0]),
50  
-					self._tx_reg.eq(Cat(self._tx_reg[1:], 0))
  31
+		tx_reg = Signal(BV(8))
  32
+		tx_bitcount = Signal(BV(4))
  33
+		tx_count16 = Signal(BV(4))
  34
+		tx_busy = Signal()
  35
+		sync += [
  36
+			If(self._rxtx.dev_re,
  37
+				tx_reg.eq(self._rxtx.dev_r),
  38
+				tx_bitcount.eq(0),
  39
+				tx_count16.eq(1),
  40
+				tx_busy.eq(1),
  41
+				self.tx.eq(0)
  42
+			).Elif(enable16 & tx_busy,
  43
+				tx_count16.eq(tx_count16 + 1),
  44
+				If(tx_count16 == Constant(0, BV(4)),
  45
+					tx_bitcount.eq(tx_bitcount + 1),
  46
+					If(tx_bitcount == 8,
  47
+						self.tx.eq(1)
  48
+					).Elif(tx_bitcount == 9,
  49
+						self.tx.eq(1),
  50
+						tx_busy.eq(0)
  51
+					).Else(
  52
+						self.tx.eq(tx_reg[0]),
  53
+						tx_reg.eq(Cat(tx_reg[1:], 0))
  54
+					)
51 55
 				)
52 56
 			)
53  
-		)]
  57
+		]
  58
+		
  59
+		comb += [
  60
+			self._f_thre.dev_we.eq(1),
  61
+			self._f_thre.dev_w.eq(~tx_busy)
  62
+		]
54 63
 		
55  
-		comb += [self._f_thre.dev_we.eq(1), self._f_thre.dev_w.eq(~self._tx_busy)]
56 64
 		return self.bank.get_fragment() + Fragment(comb, sync, pads={self.tx, self.rx})

0 notes on commit 3b640c4

Please sign in to comment.
Something went wrong with that request. Please try again.