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dvisampler: add RawDVISampler

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commit 4259699d7819cc12e653ee23b56c5e851f470ccf 1 parent 6307331
@sbourdeauducq sbourdeauducq authored
Showing with 38 additions and 0 deletions.
  1. +38 −0 milkymist/dvisampler/__init__.py
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38 milkymist/dvisampler/__init__.py
@@ -1,6 +1,8 @@
from migen.fhdl.structure import *
from migen.fhdl.module import Module
from migen.bank.description import *
+from migen.genlib.fifo import AsyncFIFO
+from migen.actorlib import structuring, dma_asmi, spi
from milkymist.dvisampler.edid import EDID
from milkymist.dvisampler.clocking import Clocking
@@ -64,3 +66,39 @@ def __init__(self, pads):
self.resdetection.hsync.eq(hsync),
self.resdetection.vsync.eq(vsync)
]
+
+class RawDVISampler(Module, AutoCSR):
+ def __init__(self, pads, asmiport):
+ self.submodules.edid = EDID(pads)
+ self.submodules.clocking = Clocking(pads)
+
+ invert = False
+ try:
+ s = getattr(pads, "data0")
+ except AttributeError:
+ s = getattr(pads, "data0_n")
+ invert = True
+ self.submodules.data0_cap = DataCapture(8, invert)
+ self.comb += [
+ self.data0_cap.pad.eq(s),
+ self.data0_cap.serdesstrobe.eq(self.clocking.serdesstrobe)
+ ]
+
+ fifo = AsyncFIFO(10, 1024)
+ self.add_submodule(fifo, {"write": "pix", "read": "sys"})
+ self.comb += [
+ fifo.din.eq(self.data0_cap.d),
+ fifo.we.eq(1)
+ ]
+
+ pack_factor = asmiport.hub.dw//16
+ self.submodules.packer = structuring.Pack([("word", 10), ("pad", 6)], pack_factor)
+ self.submodules.cast = structuring.Cast(self.packer.source.payload.layout, asmiport.hub.dw)
+ self.submodules.dma = spi.DMAWriteController(dma_asmi.Writer(asmiport), spi.MODE_SINGLE_SHOT)
+ self.comb += [
+ self.packer.sink.stb.eq(fifo.readable),
+ fifo.re.eq(self.packer.sink.ack),
+ self.packer.sink.payload.word.eq(fifo.dout),
+ self.packer.source.connect(self.cast.sink, match_by_position=True),
+ self.cast.source.connect(self.dma.data, match_by_position=True)
+ ]
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