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dvisampler: add RawDVISampler

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commit 4259699d7819cc12e653ee23b56c5e851f470ccf 1 parent 6307331
Sébastien Bourdeauducq authored May 04, 2013

Showing 1 changed file with 38 additions and 0 deletions. Show diff stats Hide diff stats

  1. 38  milkymist/dvisampler/__init__.py
38  milkymist/dvisampler/__init__.py
... ...
@@ -1,6 +1,8 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.fhdl.module import Module
3 3
 from migen.bank.description import *
  4
+from migen.genlib.fifo import AsyncFIFO
  5
+from migen.actorlib import structuring, dma_asmi, spi
4 6
 
5 7
 from milkymist.dvisampler.edid import EDID
6 8
 from milkymist.dvisampler.clocking import Clocking
@@ -64,3 +66,39 @@ def __init__(self, pads):
64 66
 			self.resdetection.hsync.eq(hsync),
65 67
 			self.resdetection.vsync.eq(vsync)
66 68
 		]
  69
+
  70
+class RawDVISampler(Module, AutoCSR):
  71
+	def __init__(self, pads, asmiport):
  72
+		self.submodules.edid = EDID(pads)
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+		self.submodules.clocking = Clocking(pads)
  74
+
  75
+		invert = False
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+		try:
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+			s = getattr(pads, "data0")
  78
+		except AttributeError:
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+			s = getattr(pads, "data0_n")
  80
+			invert = True
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+		self.submodules.data0_cap = DataCapture(8, invert)
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+		self.comb += [
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+			self.data0_cap.pad.eq(s),
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+			self.data0_cap.serdesstrobe.eq(self.clocking.serdesstrobe)
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+		]
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+
  87
+		fifo = AsyncFIFO(10, 1024)
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+		self.add_submodule(fifo, {"write": "pix", "read": "sys"})
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+		self.comb += [
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+			fifo.din.eq(self.data0_cap.d),
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+			fifo.we.eq(1)
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+		]
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+
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+		pack_factor = asmiport.hub.dw//16
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+		self.submodules.packer = structuring.Pack([("word", 10), ("pad", 6)], pack_factor)
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+		self.submodules.cast = structuring.Cast(self.packer.source.payload.layout, asmiport.hub.dw)
  97
+		self.submodules.dma = spi.DMAWriteController(dma_asmi.Writer(asmiport), spi.MODE_SINGLE_SHOT)
  98
+		self.comb += [
  99
+			self.packer.sink.stb.eq(fifo.readable),
  100
+			fifo.re.eq(self.packer.sink.ack),
  101
+			self.packer.sink.payload.word.eq(fifo.dout),
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+			self.packer.source.connect(self.cast.sink, match_by_position=True),
  103
+			self.cast.source.connect(self.dma.data, match_by_position=True)
  104
+		]

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