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lm32: use submodule

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1 parent 0caac22 commit 43343b131f4cc1e7ea910a89f67c8633daa2bd2c @sbourdeauducq sbourdeauducq committed Feb 24, 2013
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@@ -0,0 +1,3 @@
+[submodule "verilog/lm32/submodule"]
+ path = verilog/lm32/submodule
+ url = git://github.com/milkymist/lm32.git
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@@ -49,13 +49,14 @@ def main():
# add Verilog sources
for d in ["generic", "m1crg", "s6ddrphy", "minimac3"]:
plat.add_source_dir(os.path.join("verilog", d))
- plat.add_sources(os.path.join("verilog", "lm32"),
+ plat.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"),
"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
- "lm32_shifter.v", "lm32_multiplier_spartan6.v", "lm32_mc_arithmetic.v",
+ "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
"jtag_tap_spartan6.v")
+ plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
plat.build_cmdline(soc.get_fragment(), clock_domains=soc.crg.get_clock_domains())
@@ -1,86 +0,0 @@
-/*
- * Milkymist SoC
- * Copyright (c) 2010 Michael Walle
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-module jtag_cores (
- input [7:0] reg_d,
- input [2:0] reg_addr_d,
- output reg_update,
- output [7:0] reg_q,
- output [2:0] reg_addr_q,
- output jtck,
- output jrstn
-);
-
-wire tck;
-wire tdi;
-wire tdo;
-wire shift;
-wire update;
-wire reset;
-
-jtag_tap jtag_tap (
- .tck(tck),
- .tdi(tdi),
- .tdo(tdo),
- .shift(shift),
- .update(update),
- .reset(reset)
-);
-
-reg [10:0] jtag_shift;
-reg [10:0] jtag_latched;
-
-always @(posedge tck or posedge reset)
-begin
- if(reset)
- jtag_shift <= 11'b0;
- else begin
- if(shift)
- jtag_shift <= {tdi, jtag_shift[10:1]};
- else
- jtag_shift <= {reg_d, reg_addr_d};
- end
-end
-
-assign tdo = jtag_shift[0];
-
-always @(posedge reg_update or posedge reset)
-begin
- if(reset)
- jtag_latched <= 11'b0;
- else
- jtag_latched <= jtag_shift;
-end
-
-assign reg_update = update;
-assign reg_q = jtag_latched[10:3];
-assign reg_addr_q = jtag_latched[2:0];
-assign jtck = tck;
-assign jrstn = ~reset;
-
-endmodule
@@ -1,60 +0,0 @@
-/*
- * Milkymist SoC
- * Copyright (c) 2010 Michael Walle
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-module jtag_tap(
- output tck,
- output tdi,
- input tdo,
- output shift,
- output update,
- output reset
-);
-
-wire g_shift;
-wire g_update;
-
-assign shift = g_shift & sel;
-assign update = g_update & sel;
-
-BSCAN_SPARTAN6 #(
- .JTAG_CHAIN(1)
-) bscan (
- .CAPTURE(),
- .DRCK(tck),
- .RESET(reset),
- .RUNTEST(),
- .SEL(sel),
- .SHIFT(g_shift),
- .TCK(),
- .TDI(tdi),
- .TMS(),
- .UPDATE(g_update),
- .TDO(tdo)
-);
-
-endmodule
@@ -1,136 +0,0 @@
-// ==================================================================
-// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-// ------------------------------------------------------------------
-// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// ------------------------------------------------------------------
-//
-// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
-//
-// Permission:
-//
-// Lattice Semiconductor grants permission to use this code
-// pursuant to the terms of the Lattice Semiconductor Corporation
-// Open Source License Agreement.
-//
-// Disclaimer:
-//
-// Lattice Semiconductor provides no warranty regarding the use or
-// functionality of this code. It is the user's responsibility to
-// verify the user's design for consistency and functionality through
-// the use of formal verification methods.
-//
-// --------------------------------------------------------------------
-//
-// Lattice Semiconductor Corporation
-// 5555 NE Moore Court
-// Hillsboro, OR 97214
-// U.S.A
-//
-// TEL: 1-800-Lattice (USA and Canada)
-// 503-286-8001 (other locations)
-//
-// web: http://www.latticesemi.com/
-// email: techsupport@latticesemi.com
-//
-// --------------------------------------------------------------------
-// FILE DETAILS
-// Project : LatticeMico32
-// File : lm32_adder.v
-// Title : Integer adder / subtractor with comparison flag generation
-// Dependencies : lm32_include.v
-// Version : 6.1.17
-// : Initial Release
-// Version : 7.0SP2, 3.0
-// : No Change
-// Version : 3.1
-// : No Change
-// =============================================================================
-
-`include "lm32_include.v"
-
-/////////////////////////////////////////////////////
-// Module interface
-/////////////////////////////////////////////////////
-
-module lm32_adder (
- // ----- Inputs -------
- adder_op_x,
- adder_op_x_n,
- operand_0_x,
- operand_1_x,
- // ----- Outputs -------
- adder_result_x,
- adder_carry_n_x,
- adder_overflow_x
- );
-
-/////////////////////////////////////////////////////
-// Inputs
-/////////////////////////////////////////////////////
-
-input adder_op_x; // Operating to perform, 0 for addition, 1 for subtraction
-input adder_op_x_n; // Inverted version of adder_op_x
-input [`LM32_WORD_RNG] operand_0_x; // Operand to add, or subtract from
-input [`LM32_WORD_RNG] operand_1_x; // Opearnd to add, or subtract by
-
-/////////////////////////////////////////////////////
-// Outputs
-/////////////////////////////////////////////////////
-
-output [`LM32_WORD_RNG] adder_result_x; // Result of addition or subtraction
-wire [`LM32_WORD_RNG] adder_result_x;
-output adder_carry_n_x; // Inverted carry
-wire adder_carry_n_x;
-output adder_overflow_x; // Indicates if overflow occured, only valid for subtractions
-reg adder_overflow_x;
-
-/////////////////////////////////////////////////////
-// Internal nets and registers
-/////////////////////////////////////////////////////
-
-wire a_sign; // Sign (i.e. positive or negative) of operand 0
-wire b_sign; // Sign of operand 1
-wire result_sign; // Sign of result
-
-/////////////////////////////////////////////////////
-// Instantiations
-/////////////////////////////////////////////////////
-
-lm32_addsub addsub (
- // ----- Inputs -----
- .DataA (operand_0_x),
- .DataB (operand_1_x),
- .Cin (adder_op_x),
- .Add_Sub (adder_op_x_n),
- // ----- Ouputs -----
- .Result (adder_result_x),
- .Cout (adder_carry_n_x)
- );
-
-/////////////////////////////////////////////////////
-// Combinational Logic
-/////////////////////////////////////////////////////
-
-// Extract signs of operands and result
-
-assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1];
-assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1];
-assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1];
-
-// Determine whether an overflow occured when performing a subtraction
-
-always @(*)
-begin
- // +ve - -ve = -ve -> overflow
- // -ve - +ve = +ve -> overflow
- if ( (!a_sign & b_sign & result_sign)
- || (a_sign & !b_sign & !result_sign)
- )
- adder_overflow_x = `TRUE;
- else
- adder_overflow_x = `FALSE;
-end
-
-endmodule
-
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