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lm32: use submodule

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commit 43343b131f4cc1e7ea910a89f67c8633daa2bd2c 1 parent 0caac22
Sébastien Bourdeauducq authored
3  .gitmodules
... ...
@@ -0,0 +1,3 @@
  1
+[submodule "verilog/lm32/submodule"]
  2
+	path = verilog/lm32/submodule
  3
+	url = git://github.com/milkymist/lm32.git
5  build.py
@@ -49,13 +49,14 @@ def main():
49 49
 	# add Verilog sources
50 50
 	for d in ["generic", "m1crg", "s6ddrphy", "minimac3"]:
51 51
 		plat.add_source_dir(os.path.join("verilog", d))
52  
-	plat.add_sources(os.path.join("verilog", "lm32"), 
  52
+	plat.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"), 
53 53
 		"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
54 54
 		"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
55  
-		"lm32_shifter.v", "lm32_multiplier_spartan6.v", "lm32_mc_arithmetic.v",
  55
+		"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
56 56
 		"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
57 57
 		"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
58 58
 		"jtag_tap_spartan6.v")
  59
+	plat.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
59 60
 	
60 61
 	plat.build_cmdline(soc.get_fragment(), clock_domains=soc.crg.get_clock_domains())
61 62
 
86  verilog/lm32/jtag_cores.v
... ...
@@ -1,86 +0,0 @@
1  
-/*
2  
- * Milkymist SoC
3  
- * Copyright (c) 2010 Michael Walle
4  
- * All rights reserved.
5  
- *
6  
- * Redistribution and use in source and binary forms, with or without
7  
- * modification, are permitted provided that the following conditions
8  
- * are met:
9  
- * 1. Redistributions of source code must retain the above copyright
10  
- *    notice, this list of conditions and the following disclaimer.
11  
- * 2. Redistributions in binary form must reproduce the above copyright
12  
- *    notice, this list of conditions and the following disclaimer in the
13  
- *    documentation and/or other materials provided with the distribution.
14  
- * 3. The name of the author may not be used to endorse or promote products
15  
- *    derived from this software without specific prior written permission.
16  
- *
17  
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18  
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19  
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20  
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21  
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22  
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26  
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  
- */
28  
-
29  
-module jtag_cores (
30  
-    input [7:0] reg_d,
31  
-    input [2:0] reg_addr_d,
32  
-    output reg_update,
33  
-    output [7:0] reg_q,
34  
-    output [2:0] reg_addr_q,
35  
-    output jtck,
36  
-    output jrstn
37  
-);
38  
-
39  
-wire tck;
40  
-wire tdi;
41  
-wire tdo;
42  
-wire shift;
43  
-wire update;
44  
-wire reset;
45  
-
46  
-jtag_tap jtag_tap (
47  
-	.tck(tck),
48  
-	.tdi(tdi),
49  
-	.tdo(tdo),
50  
-	.shift(shift),
51  
-	.update(update),
52  
-	.reset(reset)
53  
-);
54  
-
55  
-reg [10:0] jtag_shift;
56  
-reg [10:0] jtag_latched;
57  
-
58  
-always @(posedge tck or posedge reset)
59  
-begin
60  
-	if(reset)
61  
-		jtag_shift <= 11'b0;
62  
-	else begin
63  
-		if(shift)
64  
-			jtag_shift <= {tdi, jtag_shift[10:1]};
65  
-		else
66  
-			jtag_shift <= {reg_d, reg_addr_d};
67  
-	end
68  
-end
69  
-
70  
-assign tdo = jtag_shift[0];
71  
-
72  
-always @(posedge reg_update or posedge reset)
73  
-begin
74  
-	if(reset)
75  
-		jtag_latched <= 11'b0;
76  
-	else
77  
-		jtag_latched <= jtag_shift;
78  
-end
79  
-
80  
-assign reg_update = update;
81  
-assign reg_q = jtag_latched[10:3];
82  
-assign reg_addr_q = jtag_latched[2:0];
83  
-assign jtck = tck;
84  
-assign jrstn = ~reset;
85  
-
86  
-endmodule
60  verilog/lm32/jtag_tap_spartan6.v
... ...
@@ -1,60 +0,0 @@
1  
-/*
2  
- * Milkymist SoC
3  
- * Copyright (c) 2010 Michael Walle
4  
- * All rights reserved.
5  
- *
6  
- * Redistribution and use in source and binary forms, with or without
7  
- * modification, are permitted provided that the following conditions
8  
- * are met:
9  
- * 1. Redistributions of source code must retain the above copyright
10  
- *    notice, this list of conditions and the following disclaimer.
11  
- * 2. Redistributions in binary form must reproduce the above copyright
12  
- *    notice, this list of conditions and the following disclaimer in the
13  
- *    documentation and/or other materials provided with the distribution.
14  
- * 3. The name of the author may not be used to endorse or promote products
15  
- *    derived from this software without specific prior written permission.
16  
- *
17  
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18  
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19  
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20  
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21  
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22  
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26  
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  
- */
28  
-
29  
-module jtag_tap(
30  
-	output tck,
31  
-	output tdi,
32  
-	input tdo,
33  
-	output shift,
34  
-	output update,
35  
-	output reset
36  
-);
37  
-
38  
-wire g_shift;
39  
-wire g_update;
40  
-
41  
-assign shift = g_shift & sel;
42  
-assign update = g_update & sel;
43  
-
44  
-BSCAN_SPARTAN6 #(
45  
-	.JTAG_CHAIN(1)
46  
-) bscan (
47  
-	.CAPTURE(),
48  
-	.DRCK(tck),
49  
-	.RESET(reset),
50  
-	.RUNTEST(),
51  
-	.SEL(sel),
52  
-	.SHIFT(g_shift),
53  
-	.TCK(),
54  
-	.TDI(tdi),
55  
-	.TMS(),
56  
-	.UPDATE(g_update),
57  
-	.TDO(tdo)
58  
-);
59  
-
60  
-endmodule
136  verilog/lm32/lm32_adder.v
... ...
@@ -1,136 +0,0 @@
1  
-//   ==================================================================
2  
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3  
-//   ------------------------------------------------------------------
4  
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5  
-//   ALL RIGHTS RESERVED 
6  
-//   ------------------------------------------------------------------
7  
-//
8  
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9  
-//
10  
-//   Permission:
11  
-//
12  
-//      Lattice Semiconductor grants permission to use this code
13  
-//      pursuant to the terms of the Lattice Semiconductor Corporation
14  
-//      Open Source License Agreement.  
15  
-//
16  
-//   Disclaimer:
17  
-//
18  
-//      Lattice Semiconductor provides no warranty regarding the use or
19  
-//      functionality of this code. It is the user's responsibility to
20  
-//      verify the user's design for consistency and functionality through
21  
-//      the use of formal verification methods.
22  
-//
23  
-//   --------------------------------------------------------------------
24  
-//
25  
-//                  Lattice Semiconductor Corporation
26  
-//                  5555 NE Moore Court
27  
-//                  Hillsboro, OR 97214
28  
-//                  U.S.A
29  
-//
30  
-//                  TEL: 1-800-Lattice (USA and Canada)
31  
-//                         503-286-8001 (other locations)
32  
-//
33  
-//                  web: http://www.latticesemi.com/
34  
-//                  email: techsupport@latticesemi.com
35  
-//
36  
-//   --------------------------------------------------------------------
37  
-//                         FILE DETAILS
38  
-// Project          : LatticeMico32
39  
-// File             : lm32_adder.v
40  
-// Title            : Integer adder / subtractor with comparison flag generation 
41  
-// Dependencies     : lm32_include.v
42  
-// Version          : 6.1.17
43  
-//                  : Initial Release
44  
-// Version          : 7.0SP2, 3.0
45  
-//                  : No Change
46  
-// Version          : 3.1
47  
-//                  : No Change
48  
-// =============================================================================
49  
-
50  
-`include "lm32_include.v"
51  
-
52  
-/////////////////////////////////////////////////////
53  
-// Module interface
54  
-/////////////////////////////////////////////////////
55  
-
56  
-module lm32_adder (
57  
-    // ----- Inputs -------
58  
-    adder_op_x,
59  
-    adder_op_x_n,
60  
-    operand_0_x,
61  
-    operand_1_x,
62  
-    // ----- Outputs -------
63  
-    adder_result_x,
64  
-    adder_carry_n_x,
65  
-    adder_overflow_x
66  
-    );
67  
-
68  
-/////////////////////////////////////////////////////
69  
-// Inputs
70  
-/////////////////////////////////////////////////////
71  
-
72  
-input adder_op_x;                                       // Operating to perform, 0 for addition, 1 for subtraction
73  
-input adder_op_x_n;                                     // Inverted version of adder_op_x
74  
-input [`LM32_WORD_RNG] operand_0_x;                     // Operand to add, or subtract from
75  
-input [`LM32_WORD_RNG] operand_1_x;                     // Opearnd to add, or subtract by
76  
-
77  
-/////////////////////////////////////////////////////
78  
-// Outputs
79  
-/////////////////////////////////////////////////////
80  
-
81  
-output [`LM32_WORD_RNG] adder_result_x;                 // Result of addition or subtraction
82  
-wire   [`LM32_WORD_RNG] adder_result_x;
83  
-output adder_carry_n_x;                                 // Inverted carry
84  
-wire   adder_carry_n_x;
85  
-output adder_overflow_x;                                // Indicates if overflow occured, only valid for subtractions
86  
-reg    adder_overflow_x;
87  
-    
88  
-/////////////////////////////////////////////////////
89  
-// Internal nets and registers 
90  
-/////////////////////////////////////////////////////
91  
-
92  
-wire a_sign;                                            // Sign (i.e. positive or negative) of operand 0
93  
-wire b_sign;                                            // Sign of operand 1
94  
-wire result_sign;                                       // Sign of result
95  
-
96  
-/////////////////////////////////////////////////////
97  
-// Instantiations 
98  
-/////////////////////////////////////////////////////
99  
-
100  
-lm32_addsub addsub (
101  
-    // ----- Inputs -----
102  
-    .DataA          (operand_0_x), 
103  
-    .DataB          (operand_1_x), 
104  
-    .Cin            (adder_op_x), 
105  
-    .Add_Sub        (adder_op_x_n), 
106  
-    // ----- Ouputs -----
107  
-    .Result         (adder_result_x), 
108  
-    .Cout           (adder_carry_n_x)
109  
-    );
110  
-
111  
-/////////////////////////////////////////////////////
112  
-// Combinational Logic
113  
-/////////////////////////////////////////////////////
114  
-
115  
-// Extract signs of operands and result
116  
-
117  
-assign a_sign = operand_0_x[`LM32_WORD_WIDTH-1];
118  
-assign b_sign = operand_1_x[`LM32_WORD_WIDTH-1];
119  
-assign result_sign = adder_result_x[`LM32_WORD_WIDTH-1];
120  
-
121  
-// Determine whether an overflow occured when performing a subtraction
122  
-
123  
-always @(*)
124  
-begin    
125  
-    //  +ve - -ve = -ve -> overflow
126  
-    //  -ve - +ve = +ve -> overflow
127  
-    if  (   (!a_sign & b_sign & result_sign)
128  
-         || (a_sign & !b_sign & !result_sign)
129  
-        )
130  
-        adder_overflow_x = `TRUE;
131  
-    else
132  
-        adder_overflow_x = `FALSE;
133  
-end
134  
-    
135  
-endmodule
136  
-
95  verilog/lm32/lm32_addsub.v
... ...
@@ -1,95 +0,0 @@
1  
-//   ==================================================================
2  
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3  
-//   ------------------------------------------------------------------
4  
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5  
-//   ALL RIGHTS RESERVED 
6  
-//   ------------------------------------------------------------------
7  
-//
8  
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9  
-//
10  
-//   Permission:
11  
-//
12  
-//      Lattice Semiconductor grants permission to use this code
13  
-//      pursuant to the terms of the Lattice Semiconductor Corporation
14  
-//      Open Source License Agreement.  
15  
-//
16  
-//   Disclaimer:
17  
-//
18  
-//      Lattice Semiconductor provides no warranty regarding the use or
19  
-//      functionality of this code. It is the user's responsibility to
20  
-//      verify the user's design for consistency and functionality through
21  
-//      the use of formal verification methods.
22  
-//
23  
-//   --------------------------------------------------------------------
24  
-//
25  
-//                  Lattice Semiconductor Corporation
26  
-//                  5555 NE Moore Court
27  
-//                  Hillsboro, OR 97214
28  
-//                  U.S.A
29  
-//
30  
-//                  TEL: 1-800-Lattice (USA and Canada)
31  
-//                         503-286-8001 (other locations)
32  
-//
33  
-//                  web: http://www.latticesemi.com/
34  
-//                  email: techsupport@latticesemi.com
35  
-//
36  
-//   --------------------------------------------------------------------
37  
-//                         FILE DETAILS
38  
-// Project          : LatticeMico32
39  
-// File             : lm32_addsub.v
40  
-// Title            : PMI adder/subtractor.
41  
-// Version          : 6.1.17
42  
-//                  : Initial Release
43  
-// Version          : 7.0SP2, 3.0
44  
-//                  : No Change
45  
-// Version          : 3.1
46  
-//                  : No Change
47  
-// =============================================================================
48  
-
49  
-`include "lm32_include.v"
50  
-
51  
-/////////////////////////////////////////////////////
52  
-// Module interface
53  
-/////////////////////////////////////////////////////
54  
-
55  
-module lm32_addsub (
56  
-    // ----- Inputs -------
57  
-    DataA, 
58  
-    DataB, 
59  
-    Cin, 
60  
-    Add_Sub, 
61  
-    // ----- Outputs -------
62  
-    Result, 
63  
-    Cout
64  
-    );
65  
-
66  
-/////////////////////////////////////////////////////
67  
-// Inputs
68  
-/////////////////////////////////////////////////////
69  
-
70  
-input [31:0] DataA;
71  
-input [31:0] DataB;
72  
-input Cin;
73  
-input Add_Sub;
74  
-
75  
-/////////////////////////////////////////////////////
76  
-// Outputs
77  
-/////////////////////////////////////////////////////
78  
-
79  
-output [31:0] Result;
80  
-wire   [31:0] Result;
81  
-output Cout;
82  
-wire   Cout;
83  
-
84  
-/////////////////////////////////////////////////////
85  
-// Instantiations
86  
-///////////////////////////////////////////////////// 
87  
-
88  
-// Modified for Milkymist: removed non-portable instantiated block
89  
-	     wire [32:0] tmp_addResult = DataA + DataB + Cin;
90  
-	     wire [32:0] tmp_subResult = DataA - DataB - !Cin;   
91  
-   
92  
-	     assign  Result = (Add_Sub == 1) ? tmp_addResult[31:0] : tmp_subResult[31:0];
93  
-	     assign  Cout = (Add_Sub == 1) ? tmp_addResult[32] : !tmp_subResult[32];
94  
-
95  
-endmodule
167  verilog/lm32/lm32_config.v
@@ -2,39 +2,186 @@
2 2
 `else
3 3
 `define LM32_CONFIG_V
4 4
 
  5
+//
  6
+// EXCEPTION VECTORS BASE ADDRESS
  7
+//
  8
+
  9
+// Base address for exception vectors
5 10
 `define CFG_EBA_RESET 32'h00860000
  11
+
  12
+// Base address for the debug exception vectors. If the DC_RE flag is
  13
+// set or the at_debug signal is asserted (see CFG_ALTERNATE_EBA) this
  14
+// will also be used for normal exception vectors.
6 15
 `define CFG_DEBA_RESET 32'h10000000
7 16
 
8  
-`define CFG_PL_MULTIPLY_ENABLED
9  
-`define CFG_PL_BARREL_SHIFT_ENABLED
  17
+// Enable exception vector remapping by external signal
  18
+//`define CFG_ALTERNATE_EBA
  19
+
  20
+
  21
+//
  22
+// ALU OPTIONS
  23
+//
  24
+
  25
+// Enable sign-extension instructions
10 26
 `define CFG_SIGN_EXTEND_ENABLED
  27
+
  28
+// Shifter
  29
+// You may either enable the piplined or the multi-cycle barrel
  30
+// shifter. The multi-cycle shifter will stall the pipeline until
  31
+// the result is available after 32 cycles.
  32
+// If both options are disabled, only "right shift by one bit" is
  33
+// available.
  34
+//`define CFG_MC_BARREL_SHIFT_ENABLED
  35
+`define CFG_PL_BARREL_SHIFT_ENABLED
  36
+
  37
+// Multiplier
  38
+// The multiplier is available either in a multi-cycle version or
  39
+// in a pipelined one. The multi-cycle multiplier stalls the pipe
  40
+// for 32 cycles. If both options are disabled, multiply operations
  41
+// are not supported.
  42
+//`define CFG_MC_MULTIPLY_ENABLED
  43
+`define CFG_PL_MULTIPLY_ENABLED
  44
+
  45
+// Enable the multi-cycle divider. Stalls the pipe until the result
  46
+// is ready after 32 cycles. If disabled, the divide operation is not
  47
+// supported.
11 48
 `define CFG_MC_DIVIDE_ENABLED
12  
-`define CFG_EBR_POSEDGE_REGISTER_FILE
13 49
 
  50
+
  51
+//
  52
+// INTERRUPTS
  53
+//
  54
+
  55
+// Enable support for 32 hardware interrupts
  56
+`define CFG_INTERRUPTS_ENABLED
  57
+
  58
+// Enable level-sensitive interrupts. The interrupt line status is
  59
+// reflected in the IP register, which is then read-only.
  60
+`define CFG_LEVEL_SENSITIVE_INTERRUPTS
  61
+
  62
+
  63
+//
  64
+// USER INSTRUCTION
  65
+//
  66
+
  67
+// Enable support for the user opcode.
  68
+//`define CFG_USER_ENABLED
  69
+
  70
+
  71
+//
  72
+// MEMORY MANAGEMENT UNIT
  73
+//
  74
+
  75
+// Enable instruction and data translation lookaside buffers and
  76
+// restricted user mode.
  77
+//`define CFG_MMU_ENABLED
  78
+
  79
+
  80
+//
  81
+// CACHE
  82
+//
  83
+
  84
+// Instruction cache
14 85
 `define CFG_ICACHE_ENABLED
15 86
 `define CFG_ICACHE_ASSOCIATIVITY   1
16 87
 `define CFG_ICACHE_SETS            256
17 88
 `define CFG_ICACHE_BYTES_PER_LINE  16
18  
-`define CFG_ICACHE_BASE_ADDRESS    32'h0
  89
+`define CFG_ICACHE_BASE_ADDRESS    32'h00000000
19 90
 `define CFG_ICACHE_LIMIT           32'h7fffffff
20 91
 
  92
+// Data cache
21 93
 `define CFG_DCACHE_ENABLED
22 94
 `define CFG_DCACHE_ASSOCIATIVITY   1
23 95
 `define CFG_DCACHE_SETS            256
24 96
 `define CFG_DCACHE_BYTES_PER_LINE  16
25  
-`define CFG_DCACHE_BASE_ADDRESS    32'h0
  97
+`define CFG_DCACHE_BASE_ADDRESS    32'h00000000
26 98
 `define CFG_DCACHE_LIMIT           32'h7fffffff
27 99
 
28  
-// Enable Debugging
  100
+
  101
+//
  102
+// DEBUG OPTION
  103
+//
  104
+
  105
+// Globally enable debugging
  106
+//`define CFG_DEBUG_ENABLED
  107
+
  108
+// Enable the hardware JTAG debugging interface.
  109
+// Note: to use this, there must be a special JTAG module for your
  110
+//       device. At the moment, there is only support for the
  111
+//       Spartan-6.
29 112
 //`define CFG_JTAG_ENABLED
  113
+
  114
+// JTAG UART is a communication channel which uses JTAG to transmit
  115
+// and receive bytes to and from the host computer.
30 116
 //`define CFG_JTAG_UART_ENABLED
31  
-//`define CFG_DEBUG_ENABLED
  117
+
  118
+// Enable reading and writing to the memory and writing CSRs using
  119
+// the JTAG interface.
32 120
 //`define CFG_HW_DEBUG_ENABLED
  121
+
  122
+// Number of hardware watchpoints, max. 4
  123
+//`define CFG_WATCHPOINTS 32'h4
  124
+
  125
+// Enable hardware breakpoints
33 126
 //`define CFG_ROM_DEBUG_ENABLED
  127
+
  128
+// Number of hardware breakpoints, max. 4
34 129
 //`define CFG_BREAKPOINTS 32'h4
35  
-//`define CFG_WATCHPOINTS 32'h4
  130
+
  131
+// Put the processor into debug mode by an external signal. That is,
  132
+// raise a breakpoint exception. This is useful if you have a debug
  133
+// monitor and a serial line and you want to trap into the monitor on a
  134
+// BREAK symbol on the serial line.
36 135
 //`define CFG_EXTERNAL_BREAK_ENABLED
37  
-//`define CFG_GDBSTUB_ENABLED
  136
+
  137
+
  138
+//
  139
+// REGISTER FILE
  140
+//
  141
+
  142
+// The following option explicitly infers block RAM for the register
  143
+// file. There is extra logic to avoid parallel writes and reads.
  144
+// Normally, if your synthesizer is smart enough, this should not be
  145
+// necessary because it will automatically infer block RAM for you.
  146
+//`define CFG_EBR_POSEDGE_REGISTER_FILE
  147
+
  148
+// Explicitly infers block RAM, too. But it uses two different clocks,
  149
+// one being shifted by 180deg, for the read and write port. Therefore,
  150
+// no additional logic to avoid the parallel write/reads.
  151
+//`define CFG_EBR_NEGEDGE_REGISTER_FILE
  152
+
  153
+
  154
+//
  155
+// MISCELLANEOUS
  156
+//
  157
+
  158
+// Exceptions on wishbone bus errors
  159
+//`define CFG_BUS_ERRORS_ENABLED
  160
+
  161
+// Enable the cycle counter
  162
+`define CFG_CYCLE_COUNTER_ENABLED
  163
+
  164
+// Embedded instruction ROM using on-chip block RAM
  165
+//`define CFG_IROM_ENABLED
  166
+//`define CFG_IROM_INIT_FILE     "NONE"
  167
+//`define CFG_IROM_BASE_ADDRESS  32'h10000000
  168
+//`define CFG_IROM_LIMIT         32'h10000fff
  169
+
  170
+// Embedded data RAM using on-chip block RAM
  171
+//`define CFG_DRAM_ENABLED
  172
+//`define CFG_DRAM_INIT_FILE     "NONE"
  173
+//`define CFG_DRAM_BASE_ADDRESS  32'h20000000
  174
+//`define CFG_DRAM_LIMIT         32'h20000fff
  175
+
  176
+// Trace unit
  177
+//`define CFG_TRACE_ENABLED
  178
+
  179
+// Resolve unconditional branches already in the X stage (UNTESTED!)
  180
+//`define CFG_FAST_UNCONDITIONAL_BRANCH
  181
+
  182
+// log2 function
  183
+// If your simulator/synthesizer does not support the $clog2 system
  184
+// function you can use a constant function instead.
38 185
 
39 186
 function integer clog2;
40 187
   input integer value;
@@ -47,4 +194,6 @@ endfunction
47 194
 
48 195
 `define CLOG2 clog2
49 196
 
  197
+//`define CLOG2 $clog2
  198
+
50 199
 `endif
2,767  verilog/lm32/lm32_cpu.v
... ...
@@ -1,2767 +0,0 @@
1  
-//   ==================================================================
2  
-//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3  
-//   ------------------------------------------------------------------
4  
-//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5  
-//   ALL RIGHTS RESERVED 
6  
-//   ------------------------------------------------------------------
7  
-//
8  
-//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9  
-//
10  
-//   Permission:
11  
-//
12  
-//      Lattice Semiconductor grants permission to use this code
13  
-//      pursuant to the terms of the Lattice Semiconductor Corporation
14  
-//      Open Source License Agreement.  
15  
-//
16  
-//   Disclaimer:
17  
-//
18  
-//      Lattice Semiconductor provides no warranty regarding the use or
19  
-//      functionality of this code. It is the user's responsibility to
20  
-//      verify the user's design for consistency and functionality through
21  
-//      the use of formal verification methods.
22  
-//
23  
-//   --------------------------------------------------------------------
24  
-//
25  
-//                  Lattice Semiconductor Corporation
26  
-//                  5555 NE Moore Court
27  
-//                  Hillsboro, OR 97214
28  
-//                  U.S.A
29  
-//
30  
-//                  TEL: 1-800-Lattice (USA and Canada)
31  
-//                         503-286-8001 (other locations)
32  
-//
33  
-//                  web: http://www.latticesemi.com/
34  
-//                  email: techsupport@latticesemi.com
35  
-//
36  
-//   --------------------------------------------------------------------
37  
-//                         FILE DETAILS
38  
-// Project          : LatticeMico32
39  
-// File             : lm32_cpu.v
40  
-// Title            : Top-level of CPU.
41  
-// Dependencies     : lm32_include.v
42  
-//
43  
-// Version 3.8
44  
-// 1. Feature: Support for dynamically switching EBA to DEBA via a GPIO.
45  
-// 2. Bug: EA now reports instruction that caused the data abort, rather than
46  
-//    next instruction.
47  
-//
48  
-// Version 3.4
49  
-// 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 
50  
-//    never serviced.
51  
-//    
52  
-// Version 3.3
53  
-// 1. Feature: Support for memory that is tightly coupled to processor core, and 
54  
-//    has a single-cycle access latency (same as caches). Instruction port has
55  
-//    access to a dedicated physically-mapped memory. Data port has access to
56  
-//    a dedicated physically-mapped memory. In order to be able to manipulate
57  
-//    values in both these memories via the debugger, these memories also
58  
-//    interface with the data port of LM32.
59  
-// 2. Feature: Extended Configuration Register
60  
-// 3. Bug Fix: Removed port names that conflict with keywords reserved in System-
61  
-//    Verilog.
62  
-//
63  
-// Version 3.2
64  
-// 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to
65  
-//    hang. At the same time CPU fails to register data bus error exception. Bug
66  
-//    is caused because (a) data bus error exception occurs after load/store has
67  
-//    passed X stage and next sequential instruction (e.g., brk) is already in X
68  
-//    stage, and (b) data bus error exception had lower priority than, say, brk
69  
-//    exception.
70  
-// 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to
71  
-//    invalid location, CPU will fail to register data bus error exception. The
72  
-//    solution is to stall scall/eret/bret/brk instructions in D pipeline stage
73  
-//    until load/store has completed.
74  
-// 3. Feature: Enable precise identification of load/store that causes seg fault.
75  
-// 4. SYNC resets used for register file when implemented in EBRs.
76  
-//
77  
-// Version 3.1
78  
-// 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR)
79  
-//    instead of distributed memory by enabling the option in LM32 GUI. 
80  
-// 2. Feature: LM32 also adds a static branch predictor to improve branch 
81  
-//    performance. All immediate-based forward-pointing branches are predicted 
82  
-//    not-taken. All immediate-based backward-pointing branches are predicted taken.
83  
-// 
84  
-// Version 7.0SP2, 3.0
85  
-// No Change
86  
-//
87  
-// Version 6.1.17
88  
-// Initial Release
89  
-// =============================================================================
90  
-
91  
-`include "lm32_include.v"
92  
-
93  
-/////////////////////////////////////////////////////
94  
-// Module interface
95  
-/////////////////////////////////////////////////////
96  
-
97  
-module lm32_cpu (
98  
-    // ----- Inputs -------
99  
-    clk_i,
100  
-`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
101  
-    clk_n_i,
102  
-`endif    
103  
-    rst_i,
104  
-`ifdef CFG_DEBUG_ENABLED
105  
- `ifdef CFG_ALTERNATE_EBA
106  
-    at_debug,
107  
- `endif
108  
-`endif
109  
-    // From external devices
110  
-`ifdef CFG_INTERRUPTS_ENABLED
111  
-    interrupt,
112  
-`endif
113  
-    // From user logic
114  
-`ifdef CFG_USER_ENABLED
115  
-    user_result,
116  
-    user_complete,
117  
-`endif     
118  
-`ifdef CFG_JTAG_ENABLED
119  
-    // From JTAG
120  
-    jtag_clk,
121  
-    jtag_update, 
122  
-    jtag_reg_q,
123  
-    jtag_reg_addr_q,
124  
-`endif
125  
-`ifdef CFG_EXTERNAL_BREAK_ENABLED
126  
-    ext_break,
127  
-`endif
128  
-`ifdef CFG_IWB_ENABLED
129  
-    // Instruction Wishbone master
130  
-    I_DAT_I,
131  
-    I_ACK_I,
132  
-    I_ERR_I,
133  
-    I_RTY_I,
134  
-`endif
135  
-    // Data Wishbone master
136  
-    D_DAT_I,
137  
-    D_ACK_I,
138  
-    D_ERR_I,
139  
-    D_RTY_I,
140  
-    // ----- Outputs -------
141  
-`ifdef CFG_TRACE_ENABLED
142  
-    trace_pc,
143  
-    trace_pc_valid,
144  
-    trace_exception,
145  
-    trace_eid,
146  
-    trace_eret,
147  
-`ifdef CFG_DEBUG_ENABLED
148  
-    trace_bret,
149  
-`endif
150  
-`endif
151  
-`ifdef CFG_JTAG_ENABLED
152  
-    jtag_reg_d,
153  
-    jtag_reg_addr_d,
154  
-`endif
155  
-`ifdef CFG_USER_ENABLED    
156  
-    user_valid,
157  
-    user_opcode,
158  
-    user_operand_0,
159  
-    user_operand_1,
160  
-`endif    
161  
-`ifdef CFG_IWB_ENABLED
162  
-    // Instruction Wishbone master
163  
-    I_DAT_O,
164  
-    I_ADR_O,
165  
-    I_CYC_O,
166  
-    I_SEL_O,
167  
-    I_STB_O,
168  
-    I_WE_O,
169  
-    I_CTI_O,
170  
-    I_LOCK_O,
171  
-    I_BTE_O,
172  
-`endif
173  
-    // Data Wishbone master
174  
-    D_DAT_O,
175  
-    D_ADR_O,
176  
-    D_CYC_O,
177  
-    D_SEL_O,
178  
-    D_STB_O,
179  
-    D_WE_O,
180  
-    D_CTI_O,
181  
-    D_LOCK_O,
182  
-    D_BTE_O
183  
-    );
184  
-
185  
-/////////////////////////////////////////////////////
186  
-// Parameters
187  
-/////////////////////////////////////////////////////
188  
-
189  
-parameter eba_reset = `CFG_EBA_RESET;                           // Reset value for EBA CSR
190  
-`ifdef CFG_DEBUG_ENABLED
191  
-parameter deba_reset = `CFG_DEBA_RESET;                         // Reset value for DEBA CSR
192  
-`endif
193  
-
194  
-`ifdef CFG_ICACHE_ENABLED
195  
-parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
196  
-parameter icache_sets = `CFG_ICACHE_SETS;                       // Number of sets
197  
-parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE;   // Number of bytes per cache line
198  
-parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS;       // Base address of cachable memory
199  
-parameter icache_limit = `CFG_ICACHE_LIMIT;                     // Limit (highest address) of cachable memory
200  
-`else
201  
-parameter icache_associativity = 1;    
202  
-parameter icache_sets = 512;                      
203  
-parameter icache_bytes_per_line = 16;  
204  
-parameter icache_base_address = 0;      
205  
-parameter icache_limit = 0;                    
206  
-`endif
207  
-
208  
-`ifdef CFG_DCACHE_ENABLED
209  
-parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
210  
-parameter dcache_sets = `CFG_DCACHE_SETS;                       // Number of sets
211  
-parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE;   // Number of bytes per cache line
212  
-parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS;       // Base address of cachable memory
213  
-parameter dcache_limit = `CFG_DCACHE_LIMIT;                     // Limit (highest address) of cachable memory
214  
-`else
215  
-parameter dcache_associativity = 1;    
216  
-parameter dcache_sets = 512;                      
217  
-parameter dcache_bytes_per_line = 16;  
218  
-parameter dcache_base_address = 0;      
219  
-parameter dcache_limit = 0;                    
220  
-`endif
221  
-
222  
-`ifdef CFG_DEBUG_ENABLED
223  
-parameter watchpoints = `CFG_WATCHPOINTS;                       // Number of h/w watchpoint CSRs
224  
-`else
225  
-parameter watchpoints = 0;
226  
-`endif
227  
-`ifdef CFG_ROM_DEBUG_ENABLED
228  
-parameter breakpoints = `CFG_BREAKPOINTS;                       // Number of h/w breakpoint CSRs
229  
-`else
230  
-parameter breakpoints = 0;
231  
-`endif
232  
-
233  
-`ifdef CFG_INTERRUPTS_ENABLED
234  
-parameter interrupts = `CFG_INTERRUPTS;                         // Number of interrupts
235  
-`else
236  
-parameter interrupts = 0;
237  
-`endif
238  
-
239  
-/////////////////////////////////////////////////////
240  
-// Inputs
241  
-/////////////////////////////////////////////////////
242  
-
243  
-input clk_i;                                    // Clock
244  
-`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
245  
-input clk_n_i;                                  // Inverted clock
246  
-`endif    
247  
-input rst_i;                                    // Reset
248  
-
249  
-`ifdef CFG_DEBUG_ENABLED
250  
- `ifdef CFG_ALTERNATE_EBA
251  
-   input at_debug;                              // GPIO input that maps EBA to DEBA
252  
- `endif
253  
-`endif
254  
-
255  
-`ifdef CFG_INTERRUPTS_ENABLED
256  
-input [`LM32_INTERRUPT_RNG] interrupt;          // Interrupt pins
257  
-`endif
258  
-
259  
-`ifdef CFG_USER_ENABLED
260  
-input [`LM32_WORD_RNG] user_result;             // User-defined instruction result
261  
-input user_complete;                            // User-defined instruction execution is complete
262  
-`endif    
263  
-
264  
-`ifdef CFG_JTAG_ENABLED
265  
-input jtag_clk;                                 // JTAG clock
266  
-input jtag_update;                              // JTAG state machine is in data register update state
267  
-input [`LM32_BYTE_RNG] jtag_reg_q;              
268  
-input [2:0] jtag_reg_addr_q;
269  
-`endif
270  
-
271  
-`ifdef CFG_IWB_ENABLED
272  
-input [`LM32_WORD_RNG] I_DAT_I;                 // Instruction Wishbone interface read data
273  
-input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
274  
-input I_ERR_I;                                  // Instruction Wishbone interface error
275  
-input I_RTY_I;                                  // Instruction Wishbone interface retry
276  
-`endif
277  
-
278  
-input [`LM32_WORD_RNG] D_DAT_I;                 // Data Wishbone interface read data
279  
-input D_ACK_I;                                  // Data Wishbone interface acknowledgement
280  
-input D_ERR_I;                                  // Data Wishbone interface error
281  
-input D_RTY_I;                                  // Data Wishbone interface retry
282  
-
283  
-`ifdef CFG_EXTERNAL_BREAK_ENABLED
284  
-input ext_break;
285  
-`endif
286  
-
287  
-/////////////////////////////////////////////////////
288  
-// Outputs
289  
-/////////////////////////////////////////////////////
290  
-
291  
-`ifdef CFG_TRACE_ENABLED
292  
-output [`LM32_PC_RNG] trace_pc;                 // PC to trace
293  
-reg    [`LM32_PC_RNG] trace_pc;
294  
-output trace_pc_valid;                          // Indicates that a new trace PC is valid
295  
-reg    trace_pc_valid;
296  
-output trace_exception;                         // Indicates an exception has occured
297  
-reg    trace_exception;
298  
-output [`LM32_EID_RNG] trace_eid;               // Indicates what type of exception has occured
299  
-reg    [`LM32_EID_RNG] trace_eid;
300  
-output trace_eret;                              // Indicates an eret instruction has been executed
301  
-reg    trace_eret;
302  
-`ifdef CFG_DEBUG_ENABLED
303  
-output trace_bret;                              // Indicates a bret instruction has been executed
304  
-reg    trace_bret;
305  
-`endif
306  
-`endif
307  
-
308  
-`ifdef CFG_JTAG_ENABLED
309  
-output [`LM32_BYTE_RNG] jtag_reg_d;
310  
-wire   [`LM32_BYTE_RNG] jtag_reg_d;
311  
-output [2:0] jtag_reg_addr_d;
312  
-wire   [2:0] jtag_reg_addr_d;
313  
-`endif
314  
-
315  
-`ifdef CFG_USER_ENABLED
316  
-output user_valid;                              // Indicates if user_opcode is valid
317  
-wire   user_valid;
318  
-output [`LM32_USER_OPCODE_RNG] user_opcode;     // User-defined instruction opcode
319  
-reg    [`LM32_USER_OPCODE_RNG] user_opcode;
320  
-output [`LM32_WORD_RNG] user_operand_0;         // First operand for user-defined instruction
321  
-wire   [`LM32_WORD_RNG] user_operand_0;
322  
-output [`LM32_WORD_RNG] user_operand_1;         // Second operand for user-defined instruction
323  
-wire   [`LM32_WORD_RNG] user_operand_1;
324  
-`endif
325  
-
326  
-`ifdef CFG_IWB_ENABLED
327  
-output [`LM32_WORD_RNG] I_DAT_O;                // Instruction Wishbone interface write data
328  
-wire   [`LM32_WORD_RNG] I_DAT_O;
329  
-output [`LM32_WORD_RNG] I_ADR_O;                // Instruction Wishbone interface address
330  
-wire   [`LM32_WORD_RNG] I_ADR_O;
331  
-output I_CYC_O;                                 // Instruction Wishbone interface cycle
332  
-wire   I_CYC_O;
333  
-output [`LM32_BYTE_SELECT_RNG] I_SEL_O;         // Instruction Wishbone interface byte select
334  
-wire   [`LM32_BYTE_SELECT_RNG] I_SEL_O;
335  
-output I_STB_O;                                 // Instruction Wishbone interface strobe
336  
-wire   I_STB_O;
337  
-output I_WE_O;                                  // Instruction Wishbone interface write enable
338  
-wire   I_WE_O;
339  
-output [`LM32_CTYPE_RNG] I_CTI_O;               // Instruction Wishbone interface cycle type 
340  
-wire   [`LM32_CTYPE_RNG] I_CTI_O;
341  
-output I_LOCK_O;                                // Instruction Wishbone interface lock bus
342  
-wire   I_LOCK_O;
343  
-output [`LM32_BTYPE_RNG] I_BTE_O;               // Instruction Wishbone interface burst type 
344  
-wire   [`LM32_BTYPE_RNG] I_BTE_O;
345  
-`endif
346  
-
347  
-output [`LM32_WORD_RNG] D_DAT_O;                // Data Wishbone interface write data
348  
-wire   [`LM32_WORD_RNG] D_DAT_O;
349  
-output [`LM32_WORD_RNG] D_ADR_O;                // Data Wishbone interface address
350  
-wire   [`LM32_WORD_RNG] D_ADR_O;
351  
-output D_CYC_O;                                 // Data Wishbone interface cycle
352  
-wire   D_CYC_O;
353  
-output [`LM32_BYTE_SELECT_RNG] D_SEL_O;         // Data Wishbone interface byte select
354  
-wire   [`LM32_BYTE_SELECT_RNG] D_SEL_O;
355  
-output D_STB_O;                                 // Data Wishbone interface strobe
356  
-wire   D_STB_O;
357  
-output D_WE_O;                                  // Data Wishbone interface write enable
358  
-wire   D_WE_O;
359  
-output [`LM32_CTYPE_RNG] D_CTI_O;               // Data Wishbone interface cycle type 
360  
-wire   [`LM32_CTYPE_RNG] D_CTI_O;
361  
-output D_LOCK_O;                                // Date Wishbone interface lock bus
362  
-wire   D_LOCK_O;
363  
-output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type 
364  
-wire   [`LM32_BTYPE_RNG] D_BTE_O;
365  
-
366  
-/////////////////////////////////////////////////////
367  
-// Internal nets and registers 
368  
-/////////////////////////////////////////////////////
369  
-
370  
-// Pipeline registers
371  
-
372  
-`ifdef LM32_CACHE_ENABLED
373  
-reg valid_a;                                    // Instruction in A stage is valid
374  
-`endif
375  
-reg valid_f;                                    // Instruction in F stage is valid
376  
-reg valid_d;                                    // Instruction in D stage is valid
377  
-reg valid_x;                                    // Instruction in X stage is valid
378  
-reg valid_m;                                    // Instruction in M stage is valid
379  
-reg valid_w;                                    // Instruction in W stage is valid
380  
-   
381  
-wire q_x;
382  
-wire [`LM32_WORD_RNG] immediate_d;              // Immediate operand
383  
-wire load_d;                                    // Indicates a load instruction
384  
-reg load_x;                                     
385  
-reg load_m;
386  
-wire load_q_x;
387  
-wire store_q_x;
388  
-wire store_d;                                   // Indicates a store instruction
389  
-reg store_x;
390  
-reg store_m;
391  
-wire [`LM32_SIZE_RNG] size_d;                   // Size of load/store (byte, hword, word)
392  
-reg [`LM32_SIZE_RNG] size_x;
393  
-wire branch_d;                                  // Indicates a branch instruction
394  
-wire branch_predict_d;                          // Indicates a branch is predicted
395  
-wire branch_predict_taken_d;                    // Indicates a branch is predicted taken
396  
-wire [`LM32_PC_RNG] branch_predict_address_d;   // Address to which predicted branch jumps
397  
-wire [`LM32_PC_RNG] branch_target_d;
398  
-wire bi_unconditional;
399  
-wire bi_conditional;
400  
-reg branch_x;                                   
401  
-reg branch_predict_x;
402  
-reg branch_predict_taken_x;
403  
-reg branch_m;
404  
-reg branch_predict_m;
405  
-reg branch_predict_taken_m;
406  
-wire branch_mispredict_taken_m;                 // Indicates a branch was mispredicted as taken
407  
-wire branch_flushX_m;                           // Indicates that instruction in X stage must be squashed
408  
-wire branch_reg_d;                              // Branch to register or immediate
409  
-wire [`LM32_PC_RNG] branch_offset_d;            // Branch offset for immediate branches
410  
-reg [`LM32_PC_RNG] branch_target_x;             // Address to branch to
411  
-reg [`LM32_PC_RNG] branch_target_m;
412  
-wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
413  
-wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
414  
-
415  
-wire x_result_sel_csr_d;                        // Select X stage result from CSRs
416  
-reg x_result_sel_csr_x;
417  
-`ifdef LM32_MC_ARITHMETIC_ENABLED
418  
-wire x_result_sel_mc_arith_d;                   // Select X stage result from multi-cycle arithmetic unit
419  
-reg x_result_sel_mc_arith_x;
420  
-`endif
421  
-`ifdef LM32_NO_BARREL_SHIFT    
422  
-wire x_result_sel_shift_d;                      // Select X stage result from shifter
423  
-reg x_result_sel_shift_x;
424  
-`endif
425  
-`ifdef CFG_SIGN_EXTEND_ENABLED
426  
-wire x_result_sel_sext_d;                       // Select X stage result from sign-extend logic
427  
-reg x_result_sel_sext_x;
428  
-`endif
429  
-wire x_result_sel_logic_d;                      // Select X stage result from logic op unit
430  
-reg x_result_sel_logic_x;
431  
-`ifdef CFG_USER_ENABLED
432  
-wire x_result_sel_user_d;                       // Select X stage result from user-defined logic
433  
-reg x_result_sel_user_x;
434  
-`endif
435  
-wire x_result_sel_add_d;                        // Select X stage result from adder
436  
-reg x_result_sel_add_x;
437  
-wire m_result_sel_compare_d;                    // Select M stage result from comparison logic
438  
-reg m_result_sel_compare_x;
439  
-reg m_result_sel_compare_m;
440  
-`ifdef CFG_PL_BARREL_SHIFT_ENABLED
441  
-wire m_result_sel_shift_d;                      // Select M stage result from shifter
442  
-reg m_result_sel_shift_x;
443  
-reg m_result_sel_shift_m;
444  
-`endif
445  
-wire w_result_sel_load_d;                       // Select W stage result from load/store unit
446  
-reg w_result_sel_load_x;
447  
-reg w_result_sel_load_m;
448  
-reg w_result_sel_load_w;
449  
-`ifdef CFG_PL_MULTIPLY_ENABLED
450  
-wire w_result_sel_mul_d;                        // Select W stage result from multiplier
451  
-reg w_result_sel_mul_x;
452  
-reg w_result_sel_mul_m;
453  
-reg w_result_sel_mul_w;
454  
-`endif
455  
-wire x_bypass_enable_d;                         // Whether result is bypassable in X stage
456  
-reg x_bypass_enable_x;                          
457  
-wire m_bypass_enable_d;                         // Whether result is bypassable in M stage
458  
-reg m_bypass_enable_x;                          
459  
-reg m_bypass_enable_m;
460  
-wire sign_extend_d;                             // Whether to sign-extend or zero-extend
461  
-reg sign_extend_x;
462  
-wire write_enable_d;                            // Register file write enable
463  
-reg write_enable_x;
464  
-wire write_enable_q_x;
465  
-reg write_enable_m;
466  
-wire write_enable_q_m;
467  
-reg write_enable_w;
468  
-wire write_enable_q_w;
469  
-wire read_enable_0_d;                           // Register file read enable 0
470  
-wire [`LM32_REG_IDX_RNG] read_idx_0_d;          // Register file read index 0
471  
-wire read_enable_1_d;                           // Register file read enable 1
472  
-wire [`LM32_REG_IDX_RNG] read_idx_1_d;          // Register file read index 1
473  
-wire [`LM32_REG_IDX_RNG] write_idx_d;           // Register file write index
474  
-reg [`LM32_REG_IDX_RNG] write_idx_x;            
475  
-reg [`LM32_REG_IDX_RNG] write_idx_m;
476  
-reg [`LM32_REG_IDX_RNG] write_idx_w;
477  
-wire [`LM32_CSR_RNG] csr_d;                     // CSR read/write index
478  
-reg  [`LM32_CSR_RNG] csr_x;                  
479  
-wire [`LM32_CONDITION_RNG] condition_d;         // Branch condition
480  
-reg [`LM32_CONDITION_RNG] condition_x;          
481  
-`ifdef CFG_DEBUG_ENABLED
482  
-wire break_d;                                   // Indicates a break instruction
483  
-reg break_x;                                    
484  
-`endif
485  
-wire scall_d;                                   // Indicates a scall instruction
486  
-reg scall_x;    
487  
-wire eret_d;                                    // Indicates an eret instruction
488  
-reg eret_x;
489  
-wire eret_q_x;
490  
-reg eret_m;
491  
-`ifdef CFG_TRACE_ENABLED
492  
-reg eret_w;
493  
-`endif
494  
-`ifdef CFG_DEBUG_ENABLED
495  
-wire bret_d;                                    // Indicates a bret instruction
496  
-reg bret_x;
497  
-wire bret_q_x;
498  
-reg bret_m;
499  
-`ifdef CFG_TRACE_ENABLED
500  
-reg bret_w;
501  
-`endif
502  
-`endif
503  
-wire csr_write_enable_d;                        // CSR write enable
504  
-reg csr_write_enable_x;
505  
-wire csr_write_enable_q_x;
506  
-`ifdef CFG_USER_ENABLED
507  
-wire [`LM32_USER_OPCODE_RNG] user_opcode_d;     // User-defined instruction opcode
508  
-`endif
509  
-
510  
-`ifdef CFG_BUS_ERRORS_ENABLED
511  
-wire bus_error_d;                               // Indicates an bus error occured while fetching the instruction in this pipeline stage
512  
-reg bus_error_x;
513  
-reg data_bus_error_exception_m;
514  
-reg [`LM32_PC_RNG] memop_pc_w;
515  
-`endif
516  
-
517  
-reg [`LM32_WORD_RNG] d_result_0;                // Result of instruction in D stage (operand 0)
518  
-reg [`LM32_WORD_RNG] d_result_1;                // Result of instruction in D stage (operand 1)
519  
-reg [`LM32_WORD_RNG] x_result;                  // Result of instruction in X stage
520  
-reg [`LM32_WORD_RNG] m_result;                  // Result of instruction in M stage
521  
-reg [`LM32_WORD_RNG] w_result;                  // Result of instruction in W stage
522  
-
523  
-reg [`LM32_WORD_RNG] operand_0_x;               // Operand 0 for X stage instruction
524  
-reg [`LM32_WORD_RNG] operand_1_x;               // Operand 1 for X stage instruction
525  
-reg [`LM32_WORD_RNG] store_operand_x;           // Data read from register to store
526  
-reg [`LM32_WORD_RNG] operand_m;                 // Operand for M stage instruction
527  
-reg [`LM32_WORD_RNG] operand_w;                 // Operand for W stage instruction
528  
-
529  
-// To/from register file
530  
-`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
531  
-reg [`LM32_WORD_RNG] reg_data_live_0;          
532  
-reg [`LM32_WORD_RNG] reg_data_live_1;  
533  
-reg use_buf;                                    // Whether to use reg_data_live or reg_data_buf
534  
-reg [`LM32_WORD_RNG] reg_data_buf_0;
535  
-reg [`LM32_WORD_RNG] reg_data_buf_1;
536  
-`endif
537  
-`ifdef LM32_EBR_REGISTER_FILE
538  
-`else
539  
-reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1];   // Register file
540  
-`endif
541  
-wire [`LM32_WORD_RNG] reg_data_0;               // Register file read port 0 data         
542  
-wire [`LM32_WORD_RNG] reg_data_1;               // Register file read port 1 data
543  
-reg [`LM32_WORD_RNG] bypass_data_0;             // Register value 0 after bypassing
544  
-reg [`LM32_WORD_RNG] bypass_data_1;             // Register value 1 after bypassing
545  
-wire reg_write_enable_q_w;
546  
-
547  
-reg interlock;                                  // Indicates pipeline should be stalled because of a read-after-write hazzard
548  
-
549  
-wire stall_a;                                   // Stall instruction in A pipeline stage
550  
-wire stall_f;                                   // Stall instruction in F pipeline stage
551  
-wire stall_d;                                   // Stall instruction in D pipeline stage
552  
-wire stall_x;                                   // Stall instruction in X pipeline stage
553  
-wire stall_m;                                   // Stall instruction in M pipeline stage
554  
-
555  
-// To/from adder