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Add build Makefile and JTAG load script

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commit 48ddbf0c856fd0e5cbfe2fc1ad618265636d631f 1 parent c387ce7
Sébastien Bourdeauducq authored February 17, 2012
32  Makefile
... ...
@@ -0,0 +1,32 @@
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+PYTHON=python3
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+
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+all: build/soc.bit
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+
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+# We need to change to the build directory because the Xilinx tools
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+# tend to dump a mess of various files in the current directory.
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+
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+build/soc.prj build/soc.ucf:
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+	$(PYTHON) build.py
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+
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+build/soc.ngc: build/soc.prj
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+	cd build && xst -ifn ../soc.xst
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+
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+build/soc.ngd: build/soc.ngc build/soc.ucf
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+	cd build && ngdbuild -uc soc.ucf soc.ngc
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+
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+build/soc.ncd: build/soc.ngd
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+	cd build && map -ol high -w soc.ngd
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+
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+build/soc-routed.ncd: build/soc.ncd
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+	cd build && par -ol high -w soc.ncd soc-routed.ncd
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+
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+build/soc.bit build/soc.bin: build/soc-routed.ncd
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+	cd build && bitgen -g Binary:Yes -g INIT_9K:Yes -w soc-routed.ncd soc.bit
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+
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+load: build/soc.bit
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+	jtag -n load.jtag
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+
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+clean:
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+	rm -rf build/*
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+
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+.PHONY: load clean
28  build.py
@@ -21,7 +21,6 @@ def add_core_files(d, files):
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 	"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
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 	"jtag_tap_spartan6.v"])
23 23
 
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-os.system("rm -rf build/*")
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 os.chdir("build")
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 def str2file(filename, contents):
@@ -35,33 +34,8 @@ def str2file(filename, contents):
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 str2file("soc.ucf", src_ucf)
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 verilog_sources.append("build/soc.v")
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-#raise SystemExit
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-
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-# xst
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+# generate XST project file
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 xst_prj = ""
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 for s in verilog_sources:
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 	xst_prj += "verilog work ../" + s + "\n"
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 str2file("soc.prj", xst_prj)
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-str2file("soc.xst", """run
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--ifn soc.prj
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--top soc
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--ifmt MIXED
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--opt_mode SPEED
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--opt_level 2
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--resource_sharing no
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--reduce_control_sets auto
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--ofn soc.ngc
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--p xc6slx45-fgg484-2""")
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-os.system("xst -ifn soc.xst")
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-
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-# ngdbuild
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-os.system("ngdbuild -uc soc.ucf soc.ngc")
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-
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-# map
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-os.system("map -ol high -w soc.ngd")
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-
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-# par
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-os.system("par -ol high -w soc.ncd soc-routed.ncd")
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-
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-# bitgen
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-os.system("bitgen -g Binary:Yes -g INIT_9K:Yes -w soc-routed.ncd soc.bit")
5  load.jtag
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+cable milkymist
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+detect
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+instruction CFG_OUT  000100 BYPASS
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+instruction CFG_IN   000101 BYPASS
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+pld load build/soc.bit
10  soc.xst
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@@ -0,0 +1,10 @@
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+run
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+-ifn soc.prj
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+-top soc
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+-ifmt MIXED
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+-opt_mode SPEED
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+-opt_level 2
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+-resource_sharing no
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+-reduce_control_sets auto
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+-ofn soc.ngc
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+-p xc6slx45-fgg484-2

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