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s6ddrphy: clock, address and command

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commit 4c1e18a9b588cbbb6e91c2de8079ba1651e384bb 1 parent f35cd4a
Sébastien Bourdeauducq authored February 19, 2012
2  constraints.py
@@ -62,6 +62,8 @@ def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
62 62
 TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
63 63
 INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
64 64
 INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
  65
+
  66
+PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
65 67
 """
66 68
 	
67 69
 	return r
145  verilog/s6ddrphy/s6ddrphy.v
@@ -44,16 +44,147 @@ module s6ddrphy #(
44 44
 	/* DDR SDRAM pads */
45 45
 	output sd_clk_out_p,
46 46
 	output sd_clk_out_n,
47  
-	output [NUM_AD-1:0] sd_a,
48  
-	output [NUM_BA-1:0] sd_ba,
49  
-	output sd_cs_n,
50  
-	output sd_cke,
51  
-	output sd_ras_n,
52  
-	output sd_cas_n,
53  
-	output sd_we_n,
  47
+	output reg [NUM_AD-1:0] sd_a,
  48
+	output reg [NUM_BA-1:0] sd_ba,
  49
+	output reg sd_cs_n,
  50
+	output reg sd_cke,
  51
+	output reg sd_ras_n,
  52
+	output reg sd_cas_n,
  53
+	output reg sd_we_n,
54 54
 	inout [NUM_D/2-1:0] sd_dq,
55 55
 	output [NUM_D/16-1:0] sd_dm,
56 56
 	inout [NUM_D/16-1:0] sd_dqs
57 57
 );
58 58
 
  59
+/* 
  60
+ * SDRAM clock
  61
+ */
  62
+ODDR2 #(
  63
+	.DDR_ALIGNMENT("NONE"),
  64
+	.INIT(1'b0),
  65
+	.SRTYPE("SYNC")
  66
+) sd_clk_forward_p (
  67
+	.Q(sd_clk_out_p),
  68
+	.C0(clk2x_90),
  69
+	.C1(~clk2x_90),
  70
+	.CE(1'b1),
  71
+	.D0(1'b1),
  72
+	.D1(1'b0),
  73
+	.R(1'b0),
  74
+	.S(1'b0)
  75
+);
  76
+ODDR2 #(
  77
+	.DDR_ALIGNMENT("NONE"),
  78
+	.INIT(1'b0),
  79
+	.SRTYPE("SYNC")
  80
+) sd_clk_forward_n (
  81
+	.Q(sd_clk_out_n),
  82
+	.C0(clk2x_90),
  83
+	.C1(~clk2x_90),
  84
+	.CE(1'b1),
  85
+	.D0(1'b0),
  86
+	.D1(1'b1),
  87
+	.R(1'b0),
  88
+	.S(1'b0)
  89
+);
  90
+
  91
+/* 
  92
+ * Command/address
  93
+ */
  94
+
  95
+reg phase_sel;
  96
+always @(negedge clk2x_90)
  97
+	phase_sel <= sys_clk;
  98
+
  99
+reg [NUM_AD-1:0] r_dfi_address_p0;
  100
+reg [NUM_BA-1:0] r_dfi_bank_p0;
  101
+reg r_dfi_cs_n_p0;
  102
+reg r_dfi_cke_p0;
  103
+reg r_dfi_ras_n_p0;
  104
+reg r_dfi_cas_n_p0;
  105
+reg r_dfi_we_n_p0;
  106
+reg [NUM_AD-1:0] r_dfi_address_p1;
  107
+reg [NUM_BA-1:0] r_dfi_bank_p1;
  108
+reg r_dfi_cs_n_p1;
  109
+reg r_dfi_cke_p1;
  110
+reg r_dfi_ras_n_p1;
  111
+reg r_dfi_cas_n_p1;
  112
+reg r_dfi_we_n_p1;
  113
+	
  114
+always @(posedge sys_clk) begin
  115
+	r_dfi_address_p0 <= dfi_address_p0;
  116
+	r_dfi_bank_p0 <= dfi_bank_p0;
  117
+	r_dfi_cs_n_p0 <= dfi_cs_n_p0;
  118
+	r_dfi_cke_p0 <= dfi_cke_p0;
  119
+	r_dfi_ras_n_p0 <= dfi_ras_n_p0;
  120
+	r_dfi_cas_n_p0 <= dfi_cas_n_p0;
  121
+	r_dfi_we_n_p0 <= dfi_we_n_p0;
  122
+	
  123
+	r_dfi_address_p1 <= dfi_address_p1;
  124
+	r_dfi_bank_p1 <= dfi_bank_p1;
  125
+	r_dfi_cs_n_p1 <= dfi_cs_n_p1;
  126
+	r_dfi_cke_p1 <= dfi_cke_p1;
  127
+	r_dfi_ras_n_p1 <= dfi_ras_n_p1;
  128
+	r_dfi_cas_n_p1 <= dfi_cas_n_p1;
  129
+	r_dfi_we_n_p1 <= dfi_we_n_p1;
  130
+end
  131
+
  132
+reg [NUM_AD-1:0] r2_dfi_address_p0;
  133
+reg [NUM_BA-1:0] r2_dfi_bank_p0;
  134
+reg r2_dfi_cs_n_p0;
  135
+reg r2_dfi_cke_p0;
  136
+reg r2_dfi_ras_n_p0;
  137
+reg r2_dfi_cas_n_p0;
  138
+reg r2_dfi_we_n_p0;
  139
+reg [NUM_AD-1:0] r2_dfi_address_p1;
  140
+reg [NUM_BA-1:0] r2_dfi_bank_p1;
  141
+reg r2_dfi_cs_n_p1;
  142
+reg r2_dfi_cke_p1;
  143
+reg r2_dfi_ras_n_p1;
  144
+reg r2_dfi_cas_n_p1;
  145
+reg r2_dfi_we_n_p1;
  146
+	
  147
+always @(negedge clk2x_90) begin
  148
+	r2_dfi_address_p0 <= r_dfi_address_p0;
  149
+	r2_dfi_bank_p0 <= r_dfi_bank_p0;
  150
+	r2_dfi_cs_n_p0 <= r_dfi_cs_n_p0;
  151
+	r2_dfi_cke_p0 <= r_dfi_cke_p0;
  152
+	r2_dfi_ras_n_p0 <= r_dfi_ras_n_p0;
  153
+	r2_dfi_cas_n_p0 <= r_dfi_cas_n_p0;
  154
+	r2_dfi_we_n_p0 <= r_dfi_we_n_p0;
  155
+	
  156
+	r2_dfi_address_p1 <= r_dfi_address_p1;
  157
+	r2_dfi_bank_p1 <= r_dfi_bank_p1;
  158
+	r2_dfi_cs_n_p1 <= r_dfi_cs_n_p1;
  159
+	r2_dfi_cke_p1 <= r_dfi_cke_p1;
  160
+	r2_dfi_ras_n_p1 <= r_dfi_ras_n_p1;
  161
+	r2_dfi_cas_n_p1 <= r_dfi_cas_n_p1;
  162
+	r2_dfi_we_n_p1 <= r_dfi_we_n_p1;
  163
+end
  164
+
  165
+always @(posedge clk2x_90) begin
  166
+	if(phase_sel) begin
  167
+		sd_a <= r2_dfi_address_p1;
  168
+		sd_ba <= r2_dfi_bank_p1;
  169
+		sd_cs_n <= r2_dfi_cs_n_p1;
  170
+		sd_cke <= r2_dfi_cke_p1;
  171
+		sd_ras_n <= r2_dfi_ras_n_p1;
  172
+		sd_cas_n <= r2_dfi_cas_n_p1;
  173
+		sd_we_n <= r2_dfi_we_n_p1;
  174
+	end else begin
  175
+		sd_a <= r2_dfi_address_p0;
  176
+		sd_ba <= r2_dfi_bank_p0;
  177
+		sd_cs_n <= r2_dfi_cs_n_p0;
  178
+		sd_cke <= r2_dfi_cke_p0;
  179
+		sd_ras_n <= r2_dfi_ras_n_p0;
  180
+		sd_cas_n <= r2_dfi_cas_n_p0;
  181
+		sd_we_n <= r2_dfi_we_n_p0;
  182
+	end
  183
+end
  184
+
  185
+// TODO
  186
+assign sd_dq = 32'hzzzzzzzz;
  187
+assign sd_dm = 0;
  188
+assign sd_dqs = 4'hz;
  189
+ 
59 190
 endmodule

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