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Convert to new CSR API

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commit 4f4f260e76eb15259bd0e8ed03260b4fa0b11ce9 1 parent caa19f9
Sébastien Bourdeauducq authored March 30, 2013
10  cif.py
@@ -45,13 +45,13 @@ def _get_rw_functions(reg_name, reg_base, size):
45 45
 
46 46
 def get_csr_header(csr_base, bank_array, interrupt_map):
47 47
 	r = "#ifndef __HW_CSR_H\n#define __HW_CSR_H\n#include <hw/common.h>\n"
48  
-	for name, rmap in bank_array.banks:
  48
+	for name, csrs, mapaddr, rmap in bank_array.banks:
49 49
 		r += "\n/* "+name+" */\n"
50  
-		reg_base = csr_base + 0x800*rmap.address
  50
+		reg_base = csr_base + 0x800*mapaddr
51 51
 		r += "#define "+name.upper()+"_BASE "+hex(reg_base)+"\n"
52  
-		for register in rmap.description:
53  
-			nr = (register.get_size() + 7)//8
54  
-			r += _get_rw_functions(name + "_" + register.name, reg_base, nr)
  52
+		for csr in csrs:
  53
+			nr = (csr.size + 7)//8
  54
+			r += _get_rw_functions(name + "_" + csr.name, reg_base, nr)
55 55
 			reg_base += 4*nr
56 56
 		try:
57 57
 			interrupt_nr = interrupt_map[name]
22  milkymist/asmiprobe/__init__.py
@@ -6,26 +6,24 @@ class ASMIprobe(Module):
6 6
 	def __init__(self, hub, trace_depth=16):
7 7
 		slots = hub.get_slots()
8 8
 		slot_count = len(slots)
9  
-		assert(trace_depth < 256)
10  
-		assert(slot_count < 256)
11 9
 		
12  
-		self._slot_count = RegisterField(8, READ_ONLY, WRITE_ONLY)
13  
-		self._trace_depth = RegisterField(8, READ_ONLY, WRITE_ONLY)
14  
-		self._slot_status = [RegisterField(2, READ_ONLY, WRITE_ONLY, name="slot_status" + str(i)) for i in range(slot_count)]
15  
-		self._trace = [RegisterField(8, READ_ONLY, WRITE_ONLY, name="trace" + str(i)) for i in range(trace_depth)]
  10
+		self._slot_count = CSRStatus(bits_for(slot_count))
  11
+		self._trace_depth = CSRStatus(bits_for(trace_depth))
  12
+		self._slot_status = [CSRStatus(2, name="slot_status" + str(i)) for i in range(slot_count)]
  13
+		self._trace = [CSRStatus(bits_for(slot_count-1), name="trace" + str(i)) for i in range(trace_depth)]
16 14
 
17 15
 		###
18 16
 		
19 17
 		self.comb += [
20  
-			self._slot_count.field.w.eq(slot_count),
21  
-			self._trace_depth.field.w.eq(trace_depth)
  18
+			self._slot_count.status.eq(slot_count),
  19
+			self._trace_depth.status.eq(trace_depth)
22 20
 		]
23 21
 		for slot, status in zip(slots, self._slot_status):
24  
-			self.comb += status.field.w.eq(slot.state)
25  
-		shift_tags = [self._trace[n].field.w.eq(self._trace[n+1].field.w)
  22
+			self.sync += status.status.eq(slot.state)
  23
+		shift_tags = [self._trace[n].status.eq(self._trace[n+1].status)
26 24
 			for n in range(len(self._trace) - 1)]
27  
-		shift_tags.append(self._trace[-1].field.w.eq(hub.tag_call))
  25
+		shift_tags.append(self._trace[-1].status.eq(hub.tag_call))
28 26
 		self.sync += If(hub.call, *shift_tags)
29 27
 
30  
-	def get_registers(self):
  28
+	def get_csrs(self):
31 29
 		return [self._slot_count, self._trace_depth] + self._slot_status + self._trace
52  milkymist/dfii/__init__.py
@@ -3,55 +3,45 @@
3 3
 from migen.bus import dfi
4 4
 from migen.bank.description import *
5 5
 
6  
-class PhaseInjector(Module, AutoReg):
  6
+class PhaseInjector(Module, AutoCSR):
7 7
 	def __init__(self, phase):
8  
-		self._cs = Field(1, WRITE_ONLY, READ_ONLY)
9  
-		self._we = Field(1, WRITE_ONLY, READ_ONLY)
10  
-		self._cas = Field(1, WRITE_ONLY, READ_ONLY)
11  
-		self._ras = Field(1, WRITE_ONLY, READ_ONLY)
12  
-		self._wren = Field(1, WRITE_ONLY, READ_ONLY)
13  
-		self._rden = Field(1, WRITE_ONLY, READ_ONLY)
14  
-		self._command = RegisterFields(self._cs, self._we, self._cas, self._ras, self._wren, self._rden)
15  
-		self._command_issue = RegisterRaw()
16  
-		
17  
-		self._address = RegisterField(len(phase.address))
18  
-		self._baddress = RegisterField(len(phase.bank))
19  
-		
20  
-		self._wrdata = RegisterField(len(phase.wrdata))
21  
-		self._rddata = RegisterField(len(phase.rddata), READ_ONLY, WRITE_ONLY)
  8
+		self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden
  9
+		self._command_issue = CSR()
  10
+		self._address = CSRStorage(len(phase.address))
  11
+		self._baddress = CSRStorage(len(phase.bank))
  12
+		self._wrdata = CSRStorage(len(phase.wrdata))
  13
+		self._rddata = CSRStatus(len(phase.rddata))
22 14
 	
23 15
 		###
24 16
 
25 17
 		self.comb += [
26 18
 			If(self._command_issue.re,
27  
-				phase.cs_n.eq(~self._cs.r),
28  
-				phase.we_n.eq(~self._we.r),
29  
-				phase.cas_n.eq(~self._cas.r),
30  
-				phase.ras_n.eq(~self._ras.r)
  19
+				phase.cs_n.eq(~self._command.storage[0]),
  20
+				phase.we_n.eq(~self._command.storage[1]),
  21
+				phase.cas_n.eq(~self._command.storage[2]),
  22
+				phase.ras_n.eq(~self._command.storage[3])
31 23
 			).Else(
32 24
 				phase.cs_n.eq(1),
33 25
 				phase.we_n.eq(1),
34 26
 				phase.cas_n.eq(1),
35 27
 				phase.ras_n.eq(1)
36 28
 			),
37  
-			phase.address.eq(self._address.field.r),
38  
-			phase.bank.eq(self._baddress.field.r),
39  
-			phase.wrdata_en.eq(self._command_issue.re & self._wren.r),
40  
-			phase.rddata_en.eq(self._command_issue.re & self._rden.r),
41  
-			phase.wrdata.eq(self._wrdata.field.r),
  29
+			phase.address.eq(self._address.storage),
  30
+			phase.bank.eq(self._baddress.storage),
  31
+			phase.wrdata_en.eq(self._command_issue.re & self._command.storage[4]),
  32
+			phase.rddata_en.eq(self._command_issue.re & self._command.storage[5]),
  33
+			phase.wrdata.eq(self._wrdata.storage),
42 34
 			phase.wrdata_mask.eq(0)
43 35
 		]
44  
-		self.sync += If(phase.rddata_valid, self._rddata.field.w.eq(phase.rddata))
  36
+		self.sync += If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
45 37
 
46  
-class DFIInjector(Module, AutoReg):
  38
+class DFIInjector(Module, AutoCSR):
47 39
 	def __init__(self, a, ba, d, nphases=1):
48 40
 		inti = dfi.Interface(a, ba, d, nphases)
49 41
 		self.slave = dfi.Interface(a, ba, d, nphases)
50 42
 		self.master = dfi.Interface(a, ba, d, nphases)
51 43
 		
52  
-		self._sel = Field()
53  
-		self._cke = Field()
54  
-		self._control = RegisterFields(self._sel, self._cke)
  44
+		self._control = CSRStorage(2) # sel, cke
55 45
 		
56 46
 		for n, phase in enumerate(inti.phases):
57 47
 			setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
@@ -60,5 +50,5 @@ def __init__(self, a, ba, d, nphases=1):
60 50
 	
61 51
 		connect_inti = dfi.interconnect_stmts(inti, self.master)
62 52
 		connect_slave = dfi.interconnect_stmts(self.slave, self.master)
63  
-		self.comb += If(self._sel.r, *connect_slave).Else(*connect_inti)
64  
-		self.comb += [phase.cke.eq(self._cke.r) for phase in inti.phases]
  53
+		self.comb += If(self._control.storage[0], *connect_slave).Else(*connect_inti)
  54
+		self.comb += [phase.cke.eq(self._control.storage[1]) for phase in inti.phases]
2  milkymist/dvisampler/__init__.py
@@ -10,7 +10,7 @@
10 10
 from milkymist.dvisampler.chansync import ChanSync
11 11
 from milkymist.dvisampler.resdetection import ResolutionDetection
12 12
 
13  
-class DVISampler(Module, AutoReg):
  13
+class DVISampler(Module, AutoCSR):
14 14
 	def __init__(self, pads):
15 15
 		self.submodules.edid = EDID(pads)
16 16
 		self.submodules.clocking = Clocking(pads)
6  milkymist/dvisampler/chansync.py
@@ -8,12 +8,12 @@
8 8
 
9 9
 from milkymist.dvisampler.common import channel_layout
10 10
 
11  
-class ChanSync(Module, AutoReg):
  11
+class ChanSync(Module, AutoCSR):
12 12
 	def __init__(self, nchan=3, depth=8):
13 13
 		self.valid_i = Signal()
14 14
 		self.chan_synced = Signal()
15 15
 
16  
-		self._r_channels_synced = RegisterField(1, READ_ONLY, WRITE_ONLY)
  16
+		self._r_channels_synced = CSRStatus()
17 17
 
18 18
 		lst_control_starts = []
19 19
 		all_control_starts = Signal()
@@ -49,4 +49,4 @@ def __init__(self, nchan=3, depth=8):
49 49
 		self.sync.pix += If(~self.valid_i,
50 50
 				self.chan_synced.eq(0)
51 51
 			).Elif(all_control_starts, self.chan_synced.eq(1))
52  
-		self.specials += MultiReg(self.chan_synced, self._r_channels_synced.field.w)
  52
+		self.specials += MultiReg(self.chan_synced, self._r_channels_synced.status)
10  milkymist/dvisampler/charsync.py
@@ -6,14 +6,14 @@
6 6
 
7 7
 from milkymist.dvisampler.common import control_tokens
8 8
 
9  
-class CharSync(Module, AutoReg):
  9
+class CharSync(Module, AutoCSR):
10 10
 	def __init__(self, required_controls=8):
11 11
 		self.raw_data = Signal(10)
12 12
 		self.synced = Signal()
13 13
 		self.data = Signal(10)
14 14
 
15  
-		self._r_char_synced = RegisterField(1, READ_ONLY, WRITE_ONLY)
16  
-		self._r_ctl_pos = RegisterField(bits_for(9), READ_ONLY, WRITE_ONLY)
  15
+		self._r_char_synced = CSRStatus()
  16
+		self._r_ctl_pos = CSRStatus(bits_for(9))
17 17
 
18 18
 		###
19 19
 
@@ -48,7 +48,7 @@ def __init__(self, required_controls=8):
48 48
 			),
49 49
 			previous_control_position.eq(control_position)
50 50
 		]
51  
-		self.specials += MultiReg(self.synced, self._r_char_synced.field.w)
52  
-		self.specials += MultiReg(word_sel, self._r_ctl_pos.field.w)
  51
+		self.specials += MultiReg(self.synced, self._r_char_synced.status)
  52
+		self.specials += MultiReg(word_sel, self._r_ctl_pos.status)
53 53
 
54 54
 		self.sync.pix += self.data.eq(raw >> word_sel)
10  milkymist/dvisampler/clocking.py
@@ -4,10 +4,10 @@
4 4
 from migen.genlib.cdc import MultiReg
5 5
 from migen.bank.description import *
6 6
 
7  
-class Clocking(Module, AutoReg):
  7
+class Clocking(Module, AutoCSR):
8 8
 	def __init__(self, pads):
9  
-		self._r_pll_reset = RegisterField()
10  
-		self._r_locked = RegisterField(1, READ_ONLY, WRITE_ONLY)
  9
+		self._r_pll_reset = CSRStorage()
  10
+		self._r_locked = CSRStatus()
11 11
 
12 12
 		self.locked = Signal()
13 13
 		self.serdesstrobe = Signal()
@@ -42,7 +42,7 @@ def __init__(self, pads):
42 42
 			Instance.Output("LOCKED", pll_locked),
43 43
 			Instance.Input("CLKFBIN", clkfbout),
44 44
 			Instance.Input("CLKIN", pads.clk),
45  
-			Instance.Input("RST", self._r_pll_reset.field.r)
  45
+			Instance.Input("RST", self._r_pll_reset.storage)
46 46
 		)
47 47
 
48 48
 		locked_async = Signal()
@@ -62,7 +62,7 @@ def __init__(self, pads):
62 62
 		self.specials += Instance("BUFG",
63 63
 			Instance.Input("I", pll_clk3), Instance.Output("O", self._cd_pix10x.clk))
64 64
 		self.specials += MultiReg(locked_async, self.locked, "sys")
65  
-		self.comb += self._r_locked.field.w.eq(self.locked)
  65
+		self.comb += self._r_locked.status.eq(self.locked)
66 66
 
67 67
 		# sychronize pix+pix5x reset
68 68
 		pix_rst_n = 1
14  milkymist/dvisampler/datacapture.py
@@ -4,16 +4,16 @@
4 4
 from migen.genlib.cdc import MultiReg, PulseSynchronizer
5 5
 from migen.bank.description import *
6 6
 
7  
-class DataCapture(Module, AutoReg):
  7
+class DataCapture(Module, AutoCSR):
8 8
 	def __init__(self, ntbits, invert):
9 9
 		self.pad = Signal()
10 10
 		self.serdesstrobe = Signal()
11 11
 		self.d = Signal(10)
12 12
 
13  
-		self._r_dly_ctl = RegisterRaw(4)
14  
-		self._r_dly_busy = RegisterField(1, READ_ONLY, WRITE_ONLY)
15  
-		self._r_phase = RegisterField(2, READ_ONLY, WRITE_ONLY)
16  
-		self._r_phase_reset = RegisterRaw()
  13
+		self._r_dly_ctl = CSR(4)
  14
+		self._r_dly_busy = CSRStatus()
  15
+		self._r_phase = CSRStatus(2)
  16
+		self._r_phase_reset = CSR()
17 17
 
18 18
 		###
19 19
 
@@ -137,11 +137,11 @@ def __init__(self, ntbits, invert):
137 137
 			self.do_delay_rst.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[1]),
138 138
 			self.do_delay_inc.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[2]),
139 139
 			self.do_delay_dec.i.eq(self._r_dly_ctl.re & self._r_dly_ctl.r[3]),
140  
-			self._r_dly_busy.field.w.eq(sys_delay_pending)
  140
+			self._r_dly_busy.status.eq(sys_delay_pending)
141 141
 		]
142 142
 
143 143
 		# Phase detector control
144  
-		self.specials += MultiReg(Cat(too_late, too_early), self._r_phase.field.w)
  144
+		self.specials += MultiReg(Cat(too_late, too_early), self._r_phase.status)
145 145
 		self.submodules.do_reset_lateness = PulseSynchronizer("sys", "pix5x")
146 146
 		self.comb += [
147 147
 			reset_lateness.eq(self.do_reset_lateness.o),
4  milkymist/dvisampler/edid.py
@@ -4,7 +4,7 @@
4 4
 from migen.genlib.cdc import MultiReg
5 5
 from migen.genlib.fsm import FSM
6 6
 from migen.genlib.misc import chooser
7  
-from migen.bank.description import AutoReg
  7
+from migen.bank.description import AutoCSR
8 8
 
9 9
 _default_edid = [
10 10
 	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x32, 0x12, 0x2A, 0x6A, 0xBF, 0x00,
@@ -17,7 +17,7 @@
17 17
 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF,
18 18
 ]
19 19
 
20  
-class EDID(Module, AutoReg):
  20
+class EDID(Module, AutoCSR):
21 21
 	def __init__(self, pads, default=_default_edid):
22 22
 		self.specials.mem = Memory(8, 128, init=default)
23 23
 
14  milkymist/dvisampler/resdetection.py
@@ -3,15 +3,15 @@
3 3
 from migen.genlib.cdc import MultiReg
4 4
 from migen.bank.description import *
5 5
 
6  
-class ResolutionDetection(Module, AutoReg):
  6
+class ResolutionDetection(Module, AutoCSR):
7 7
 	def __init__(self, nbits=10):
8 8
 		self.hsync = Signal()
9 9
 		self.vsync = Signal()
10 10
 		self.de = Signal()
11 11
 
12  
-		self._hres = RegisterField(nbits, READ_ONLY, WRITE_ONLY)
13  
-		self._vres = RegisterField(nbits, READ_ONLY, WRITE_ONLY)
14  
-		self._de_cycles = RegisterField(2*nbits, READ_ONLY, WRITE_ONLY)
  12
+		self._hres = CSRStatus(nbits)
  13
+		self._vres = CSRStatus(nbits)
  14
+		self._de_cycles = CSRStatus(2*nbits)
15 15
 
16 16
 		###
17 17
 
@@ -50,8 +50,8 @@ def __init__(self, nbits=10):
50 50
 			If(p_hsync & (hcounter != 0), hcounter_st.eq(hcounter)),
51 51
 			If(p_vsync & (vcounter != 0), vcounter_st.eq(vcounter))
52 52
 		]
53  
-		self.specials += MultiReg(hcounter_st, self._hres.field.w)
54  
-		self.specials += MultiReg(vcounter_st, self._vres.field.w)
  53
+		self.specials += MultiReg(hcounter_st, self._hres.status)
  54
+		self.specials += MultiReg(vcounter_st, self._vres.status)
55 55
 
56 56
 		# DE
57 57
 		de_r = Signal()
@@ -68,4 +68,4 @@ def __init__(self, nbits=10):
68 68
 
69 69
 		decounter_st = Signal(2*nbits)
70 70
 		self.sync.pix += If(pn_de, decounter_st.eq(decounter))
71  
-		self.specials += MultiReg(decounter_st, self._de_cycles.field.w)
  71
+		self.specials += MultiReg(decounter_st, self._de_cycles.status)
6  milkymist/framebuffer/__init__.py
@@ -220,7 +220,7 @@ def __init__(self, pads, asmiport, simulation=False):
220 220
 		g.add_connection(vtg, fifo)
221 221
 		self.submodules._comp_actor = CompositeActor(g, debugger=False)
222 222
 		
223  
-		self._registers = fi.get_registers() + self._comp_actor.get_registers()
  223
+		self._csrs = fi.get_csrs() + self._comp_actor.get_csrs()
224 224
 		
225 225
 		# Drive pads
226 226
 		if not simulation:
@@ -233,5 +233,5 @@ def __init__(self, pads, asmiport, simulation=False):
233 233
 			]
234 234
 		self.comb += pads.psave_n.eq(1)
235 235
 
236  
-	def get_registers(self):
237  
-		return self._registers
  236
+	def get_csrs(self):
  237
+		return self._csrs
14  milkymist/identifier/__init__.py
@@ -15,16 +15,16 @@ def encode_version(version):
15 15
 		r |= int(rc)
16 16
 	return r
17 17
 
18  
-class Identifier(Module, AutoReg):
  18
+class Identifier(Module, AutoCSR):
19 19
 	def __init__(self, sysid, version, frequency):
20  
-		self._r_sysid = RegisterField(16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
21  
-		self._r_version = RegisterField(16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
22  
-		self._r_frequency = RegisterField(32, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
  20
+		self._r_sysid = CSRStatus(16)
  21
+		self._r_version = CSRStatus(16)
  22
+		self._r_frequency = CSRStatus(32)
23 23
 		
24 24
 		###
25 25
 
26 26
 		self.comb += [
27  
-			self._r_sysid.field.w.eq(sysid),
28  
-			self._r_version.field.w.eq(encode_version(version)),
29  
-			self._r_frequency.field.w.eq(frequency)
  27
+			self._r_sysid.status.eq(sysid),
  28
+			self._r_version.status.eq(encode_version(version)),
  29
+			self._r_frequency.status.eq(frequency)
30 30
 		]
14  milkymist/m1crg/__init__.py
@@ -5,7 +5,7 @@
5 5
 from migen.fhdl.module import Module
6 6
 from migen.bank.description import *
7 7
 
8  
-class M1CRG(Module, AutoReg):
  8
+class M1CRG(Module, AutoCSR):
9 9
 	def __init__(self, pads, outfreq1x):
10 10
 		self.clock_domains.cd_sys = ClockDomain()
11 11
 		self.clock_domains.cd_sys2x_270 = ClockDomain()
@@ -18,10 +18,10 @@ def __init__(self, pads, outfreq1x):
18 18
 		self.clk4x_wr_strb = Signal()
19 19
 		self.clk4x_rd_strb = Signal()
20 20
 
21  
-		self._r_cmd_data = RegisterField(10)
22  
-		self._r_send_cmd_data = RegisterRaw()
23  
-		self._r_send_go = RegisterRaw()
24  
-		self._r_status = RegisterField(3, READ_ONLY, WRITE_ONLY)
  21
+		self._r_cmd_data = CSRStorage(10)
  22
+		self._r_send_cmd_data = CSR()
  23
+		self._r_send_go = CSR()
  24
+		self._r_status = CSRStatus(3)
25 25
 
26 26
 		###
27 27
 		
@@ -74,7 +74,7 @@ def __init__(self, pads, outfreq1x):
74 74
 		self.sync += [
75 75
 			If(self._r_send_cmd_data.re,
76 76
 				remaining_bits.eq(10),
77  
-				sr.eq(self._r_cmd_data.field.r)
  77
+				sr.eq(self._r_cmd_data.storage)
78 78
 			).Elif(transmitting,
79 79
 				remaining_bits.eq(remaining_bits - 1),
80 80
 				sr.eq(sr[1:])
@@ -95,4 +95,4 @@ def __init__(self, pads, outfreq1x):
95 95
 				busy_counter.eq(busy_counter - 1)
96 96
 			)
97 97
 
98  
-		self.comb += self._r_status.field.w.eq(Cat(busy, vga_progdone, vga_locked))
  98
+		self.comb += self._r_status.status.eq(Cat(busy, vga_progdone, vga_locked))
24  milkymist/minimac3/__init__.py
@@ -7,14 +7,14 @@
7 7
 
8 8
 _count_width = 11
9 9
 
10  
-class MiniMAC(Module, AutoReg):
  10
+class MiniMAC(Module, AutoCSR):
11 11
 	def __init__(self, pads):
12 12
 		# CPU interface
13  
-		self._phy_reset = RegisterField(reset=1)
14  
-		self._rx_count_0 = RegisterField(_count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
15  
-		self._rx_count_1 = RegisterField(_count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
16  
-		self._tx_count = RegisterField(_count_width, access_dev=READ_WRITE)
17  
-		self._tx_start = RegisterRaw()
  13
+		self._phy_reset = CSRStorage(reset=1)
  14
+		self._rx_count_0 = CSRStatus(_count_width)
  15
+		self._rx_count_1 = CSRStatus(_count_width)
  16
+		self._tx_count = CSRStorage(_count_width, write_from_dev=True)
  17
+		self._tx_start = CSR()
18 18
 		
19 19
 		self.submodules.ev = EventManager()
20 20
 		self.ev.rx0 = EventSourcePulse()
@@ -35,13 +35,13 @@ def __init__(self, pads):
35 35
 		rx_pending_0_r = Signal()
36 36
 		rx_pending_1_r = Signal()
37 37
 		self.comb += [
38  
-			pads.rst_n.eq(~self._phy_reset.field.r),
  38
+			pads.rst_n.eq(~self._phy_reset.storage),
39 39
 			
40 40
 			rx_ready_0.eq(init | (rx_pending_0_r & ~rx_pending_0)),
41 41
 			rx_ready_1.eq(init | (rx_pending_1_r & ~rx_pending_1)),
42 42
 			
43  
-			self._tx_count.field.w.eq(0),
44  
-			self._tx_count.field.we.eq(self.ev.tx.trigger)
  43
+			self._tx_count.dat_w.eq(0),
  44
+			self._tx_count.we.eq(self.ev.tx.trigger)
45 45
 		]
46 46
 		self.sync += [
47 47
 			rx_pending_0_r.eq(rx_pending_0),
@@ -52,14 +52,14 @@ def __init__(self, pads):
52 52
 				Instance.Input("sys_rst", ResetSignal()),
53 53
 
54 54
 				Instance.Output("rx_done_0", self.ev.rx0.trigger),
55  
-				Instance.Output("rx_count_0", self._rx_count_0.field.w),
  55
+				Instance.Output("rx_count_0", self._rx_count_0.status),
56 56
 				Instance.Output("rx_done_1", self.ev.rx1.trigger),
57  
-				Instance.Output("rx_count_1", self._rx_count_1.field.w),
  57
+				Instance.Output("rx_count_1", self._rx_count_1.status),
58 58
 				Instance.Input("rx_ready_0", rx_ready_0),
59 59
 				Instance.Input("rx_ready_1", rx_ready_1),
60 60
 
61 61
 				Instance.Input("tx_start", self._tx_start.re),
62  
-				Instance.Input("tx_count", self._tx_count.field.r),
  62
+				Instance.Input("tx_count", self._tx_count.storage),
63 63
 				Instance.Output("tx_done", self.ev.tx.trigger),
64 64
 				
65 65
 				Instance.Input("wb_adr_i", self.membus.adr),
18  milkymist/timer/__init__.py
@@ -3,11 +3,11 @@
3 3
 from migen.bank.description import *
4 4
 from migen.bank.eventmanager import *
5 5
 
6  
-class Timer(Module, AutoReg):
  6
+class Timer(Module, AutoCSR):
7 7
 	def __init__(self, width=32):
8  
-		self._en = RegisterField()
9  
-		self._value = RegisterField(width, access_dev=READ_WRITE)
10  
-		self._reload = RegisterField(width)
  8
+		self._en = CSRStorage()
  9
+		self._value = CSRStorage(width, write_from_dev=True)
  10
+		self._reload = CSRStorage(width)
11 11
 		
12 12
 		self.submodules.ev = EventManager()
13 13
 		self.ev.zero = EventSourceLevel()
@@ -16,11 +16,11 @@ def __init__(self, width=32):
16 16
 		###
17 17
 
18 18
 		self.comb += [
19  
-			If(self._value.field.r == 0,
20  
-				self._value.field.w.eq(self._reload.field.r)
  19
+			If(self._value.storage == 0,
  20
+				self._value.dat_w.eq(self._reload.storage)
21 21
 			).Else(
22  
-				self._value.field.w.eq(self._value.field.r - 1)
  22
+				self._value.dat_w.eq(self._value.storage - 1)
23 23
 			),
24  
-			self._value.field.we.eq(self._en.field.r),
25  
-			self.ev.zero.trigger.eq(self._value.field.r != 0)
  24
+			self._value.we.eq(self._en.storage),
  25
+			self.ev.zero.trigger.eq(self._value.storage != 0)
26 26
 		]
8  milkymist/uart/__init__.py
@@ -4,10 +4,10 @@
4 4
 from migen.bank.description import *
5 5
 from migen.bank.eventmanager import *
6 6
 
7  
-class UART(Module, AutoReg):
  7
+class UART(Module, AutoCSR):
8 8
 	def __init__(self, pads, clk_freq, baud=115200):
9  
-		self._rxtx = RegisterRaw(8)
10  
-		self._divisor = RegisterField(16, reset=int(clk_freq/baud/16))
  9
+		self._rxtx = CSR(8)
  10
+		self._divisor = CSRStorage(16, reset=int(clk_freq/baud/16))
11 11
 		
12 12
 		self.submodules.ev = EventManager()
13 13
 		self.ev.tx = EventSourceLevel()
@@ -24,7 +24,7 @@ def __init__(self, pads, clk_freq, baud=115200):
24 24
 		self.sync += [
25 25
 			enable16_counter.eq(enable16_counter - 1),
26 26
 			If(enable16,
27  
-				enable16_counter.eq(self._divisor.field.r - 1))
  27
+				enable16_counter.eq(self._divisor.storage - 1))
28 28
 		]
29 29
 		
30 30
 		# TX

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