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Include Wishbone to ASMI bridge

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commit 5165ff7ec3e2428819a019eef4a4f22f4c2c2ddb 1 parent 0654bf4
Sébastien Bourdeauducq authored

Showing 1 changed file with 31 additions and 9 deletions. Show diff stats Hide diff stats

  1. 40  top.py
40  top.py
... ...
@@ -1,21 +1,30 @@
1 1
 from migen.fhdl.structure import *
2  
-from migen.fhdl import tools, verilog, autofragment
3  
-from migen.bus import wishbone, csr, wishbone2csr
  2
+from migen.fhdl import verilog, autofragment
  3
+from migen.bus import wishbone, asmibus, wishbone2asmi, csr, wishbone2csr
4 4
 
5 5
 from milkymist import m1reset, clkfx, lm32, norflash, uart, sram
6 6
 import constraints
7 7
 
  8
+MHz = 1000000
  9
+clk_freq = 80*MHz
  10
+sram_size = 4096 # in bytes
  11
+l2_size = 8192 # in bytes
  12
+
8 13
 def get():
9  
-	MHz = 1000000
10  
-	clk_freq = 80*MHz
11  
-	sram_size = 4096 # in bytes
12  
-	
13  
-	clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
14  
-	reset0 = m1reset.M1Reset()
  14
+	#
  15
+	# ASMI
  16
+	#
  17
+	asmihub0 = asmibus.Hub(24, 64, 8) # TODO: get hub from memory controller
  18
+	asmiport_wb = asmihub0.get_port()
  19
+	asmihub0.finalize()
15 20
 	
  21
+	#
  22
+	# WISHBONE
  23
+	#
16 24
 	cpu0 = lm32.LM32()
17 25
 	norflash0 = norflash.NorFlash(25, 12)
18 26
 	sram0 = sram.SRAM(sram_size//4)
  27
+	wishbone2asmi0 = wishbone2asmi.WB2ASMI(l2_size//4, asmiport_wb)
19 28
 	wishbone2csr0 = wishbone2csr.WB2CSR()
20 29
 	
21 30
 	# norflash     0x00000000 (shadow @0x80000000)
@@ -23,7 +32,7 @@ def get():
23 32
 	# USB          0x20000000 (shadow @0xa0000000)
24 33
 	# Ethernet     0x30000000 (shadow @0xb0000000)
25 34
 	# SDRAM        0x40000000 (shadow @0xc0000000)
26  
-	# CSR bridge   0x60000000 (shadow @0xe0000000)	
  35
+	# CSR bridge   0x60000000 (shadow @0xe0000000)
27 36
 	wishbonecon0 = wishbone.InterconnectShared(
28 37
 		[
29 38
 			cpu0.ibus,
@@ -31,18 +40,31 @@ def get():
31 40
 		], [
32 41
 			(binc("000"), norflash0.bus),
33 42
 			(binc("001"), sram0.bus),
  43
+			(binc("10"), wishbone2asmi0.wishbone),
34 44
 			(binc("11"), wishbone2csr0.wishbone)
35 45
 		],
36 46
 		register=True,
37 47
 		offset=1)
38 48
 	
  49
+	#
  50
+	# CSR
  51
+	#
39 52
 	uart0 = uart.UART(0, clk_freq, baud=115200)
40 53
 	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
41 54
 	
  55
+	#
  56
+	# Interrupts
  57
+	#
42 58
 	interrupts = Fragment([
43 59
 		cpu0.interrupt[0].eq(uart0.events.irq)
44 60
 	])
45 61
 	
  62
+	#
  63
+	# Housekeeping
  64
+	#
  65
+	clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
  66
+	reset0 = m1reset.M1Reset()
  67
+	
46 68
 	frag = autofragment.from_local() + interrupts
47 69
 	src_verilog, vns = verilog.convert(frag,
48 70
 		{clkfx_sys.clkin, reset0.trigger_reset},

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