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Do not use super()

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commit 51f4f920a24d2adb2db2d442fc01ae8325be5c5b 1 parent c44ff89
@sbourdeauducq sbourdeauducq authored
View
4 milkymist/asmicon/bankmachine.py
@@ -79,7 +79,7 @@ def get_fragment(self):
(slot.state == SLOT_PENDING)
))
- return Fragment(comb) + super().get_fragment()
+ return Fragment(comb) + _Selector.get_fragment(self)
class _FullSelector(_Selector):
def get_fragment(self):
@@ -149,7 +149,7 @@ def get_fragment(self):
select_stmt = If(has_mature, *best_mature).Else(select_stmt)
comb.append(select_stmt)
- return Fragment(comb, sync) + super().get_fragment()
+ return Fragment(comb, sync) + _Selector.get_fragment(self)
class _Buffer:
def __init__(self, source):
View
6 milkymist/framebuffer/__init__.py
@@ -44,11 +44,11 @@ def __init__(self, asmi_bits, length_bits, alignment_bits):
("base", asmi_bits, 0, alignment_bits),
("length", length_bits, 640*480*4, alignment_bits)
]
- super().__init__(layout, spi.MODE_CONTINUOUS)
+ spi.SingleGenerator.__init__(self, layout, spi.MODE_CONTINUOUS)
class VTG(Actor):
def __init__(self):
- super().__init__(
+ Actor.__init__(self,
("timing", Sink, [
("hres", _hbits),
("hsync_start", _hbits),
@@ -115,7 +115,7 @@ def get_fragment(self):
class FIFO(Actor):
def __init__(self):
- super().__init__(("dac", Sink, _dac_layout))
+ Actor.__init__(self, ("dac", Sink, _dac_layout))
self.vga_hsync_n = Signal()
self.vga_vsync_n = Signal()
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