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DFI injector (untested)

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commit 5bc840b9c115936862a7f38ac11a25d13833f8d5 1 parent c38de34
Sébastien Bourdeauducq authored February 17, 2012
112  milkymist/dfii/__init__.py
... ...
@@ -0,0 +1,112 @@
  1
+from migen.fhdl.structure import *
  2
+from migen.bus import dfi
  3
+from migen.bank.description import *
  4
+from migen.bank import csrgen
  5
+
  6
+def _data_en(trigger, output, delay, duration):
  7
+	dcounter = Signal(BV(4))
  8
+	dce = Signal()
  9
+	return [
  10
+		If(trigger,
  11
+			dcounter.eq(delay),
  12
+			dce.eq(1)
  13
+		).Elif(dce,
  14
+			dcounter.eq(dcounter - 1),
  15
+			If(dcounter == 0,
  16
+				If(~output,
  17
+					output.eq(1),
  18
+					dcounter.eq(duration)
  19
+				).Else(
  20
+					output.eq(0),
  21
+					dce.eq(0)
  22
+				)
  23
+			)
  24
+		)
  25
+	]
  26
+
  27
+class DFIInjector:
  28
+	def __init__(self, csr_address, a, ba, d, nphases=1):
  29
+		self._int = dfi.Interface(a, ba, d, nphases)
  30
+		self.slave = dfi.Interface(a, ba, d, nphases)
  31
+		self.master = dfi.Interface(a, ba, d, nphases)
  32
+		
  33
+		self._sel = Field("sel")
  34
+		self._cke = Field("cke")
  35
+		self._control = RegisterFields("control", [self._sel, self._cke])
  36
+		
  37
+		self._cs = Field("cs", 1, WRITE_ONLY, READ_ONLY)
  38
+		self._we = Field("we", 1, WRITE_ONLY, READ_ONLY)
  39
+		self._cas = Field("cas", 1, WRITE_ONLY, READ_ONLY)
  40
+		self._ras = Field("ras", 1, WRITE_ONLY, READ_ONLY)
  41
+		self._rddata = Field("rddata", 1, WRITE_ONLY, READ_ONLY)
  42
+		self._wrdata = Field("wrdata", 1, WRITE_ONLY, READ_ONLY)
  43
+		self._command = RegisterFields("command",
  44
+			[self._cs, self._we, self._cas, self._ras, self._rddata, self._wrdata])
  45
+		
  46
+		self._address = RegisterField("address", a)
  47
+		self._baddress = RegisterField("baddress", ba)
  48
+		
  49
+		self._rddelay = RegisterField("rddelay", 4, reset=5)
  50
+		self._rdduration = RegisterField("rdduration", 3, reset=0)
  51
+		self._wrdelay = RegisterField("wrdelay", 4, reset=3)
  52
+		self._wrduration = RegisterField("wrduration", 3, reset=0)
  53
+		
  54
+		self.bank = csrgen.Bank([
  55
+				self._control, self._command,
  56
+				self._address, self._baddress,
  57
+				self._rddelay, self._rdduration,
  58
+				self._wrdelay, self._wrduration
  59
+			], address=csr_address)
  60
+	
  61
+	def get_fragment(self):
  62
+		comb = []
  63
+		sync = []
  64
+		
  65
+		# mux
  66
+		connect_int = dfi.interconnect_stmts(self._int, self.master)
  67
+		connect_slave = dfi.interconnect_stmts(self.slave, self.master)
  68
+		comb.append(If(self._sel.r, *connect_slave).Else(*connect_int))
  69
+		
  70
+		# phases
  71
+		rddata_en = Signal()
  72
+		wrdata_en = Signal()
  73
+		for phase in self._int.phases:
  74
+			comb += [
  75
+				phase.cke.eq(self._cke.r),
  76
+				phase.rddata_en.eq(rddata_en),
  77
+				phase.wrdata_en.eq(wrdata_en)
  78
+			]
  79
+		cmdphase = self._int.phases[0]
  80
+		for phase in self._int.phases[1:]:
  81
+			comb += [
  82
+				phase.cs_n.eq(1),
  83
+				phase.we_n.eq(1),
  84
+				phase.cas_n.eq(1),
  85
+				phase.ras_n.eq(1)
  86
+				
  87
+			]
  88
+		
  89
+		# commands
  90
+		comb += [
  91
+			If(self._command.re,
  92
+				cmdphase.cs_n.eq(~self._cs.r),
  93
+				cmdphase.we_n.eq(~self._we.r),
  94
+				cmdphase.cas_n.eq(~self._cas.r),
  95
+				cmdphase.ras_n.eq(~self._ras.r)
  96
+			).Else(
  97
+				cmdphase.cs_n.eq(1),
  98
+				cmdphase.we_n.eq(1),
  99
+				cmdphase.cas_n.eq(1),
  100
+				cmdphase.ras_n.eq(1)
  101
+			)
  102
+		]
  103
+		
  104
+		# data enables
  105
+		sync += _data_en(self._command.re & self._rddata.r,
  106
+			rddata_en,
  107
+			self._rddelay.field.r, self._rdduration.field.r)
  108
+		sync += _data_en(self._command.re & self._wrdata.r,
  109
+			wrdata_en,
  110
+			self._wrdelay.field.r, self._wrduration.field.r)
  111
+		
  112
+		return Fragment(comb, sync) + self.bank.get_fragment()
46  software/include/hw/dfii.h
... ...
@@ -0,0 +1,46 @@
  1
+/*
  2
+ * Milkymist SoC (Software)
  3
+ * Copyright (C) 2012 Sebastien Bourdeauducq
  4
+ *
  5
+ * This program is free software: you can redistribute it and/or modify
  6
+ * it under the terms of the GNU General Public License as published by
  7
+ * the Free Software Foundation, version 3 of the License.
  8
+ *
  9
+ * This program is distributed in the hope that it will be useful,
  10
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12
+ * GNU General Public License for more details.
  13
+ *
  14
+ * You should have received a copy of the GNU General Public License
  15
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16
+ */
  17
+
  18
+#ifndef __HW_DFII_H
  19
+#define __HW_DFII_H
  20
+
  21
+#include <hw/common.h>
  22
+
  23
+#define CSR_DFII_CONTROL		MMPTR(0xe0001000)
  24
+
  25
+#define DFII_CONTROL_SEL		(0x01)
  26
+#define DFII_CONTROL_CKE		(0x02)
  27
+
  28
+#define CSR_DFII_COMMAND		MMPTR(0xe0001004)
  29
+
  30
+#define DFII_COMMAND_CS			(0x01)
  31
+#define DFII_COMMAND_WE			(0x02)
  32
+#define DFII_COMMAND_CAS		(0x04)
  33
+#define DFII_COMMAND_RAS		(0x08)
  34
+#define DFII_COMMAND_RDDATA		(0x10)
  35
+#define DFII_COMMAND_WRDATA		(0x20)
  36
+
  37
+#define CSR_DFII_AH			MMPTR(0xe0001008)
  38
+#define CSR_DFII_AL			MMPTR(0xe000100C)
  39
+#define CSR_DFII_BA			MMPTR(0xe0001010)
  40
+
  41
+#define CSR_DFII_RDDELAY		MMPTR(0xe0001014)
  42
+#define CSR_DFII_RDDURATION		MMPTR(0xe0001018)
  43
+#define CSR_DFII_WRDELAY		MMPTR(0xe000101C)
  44
+#define CSR_DFII_WRDURATION		MMPTR(0xe0001020)
  45
+
  46
+#endif /* __HW_DFII_H */
19  top.py
@@ -2,9 +2,9 @@
2 2
 
3 3
 from migen.fhdl.structure import *
4 4
 from migen.fhdl import verilog, autofragment
5  
-from migen.bus import wishbone, asmibus, wishbone2asmi, csr, wishbone2csr
  5
+from migen.bus import wishbone, asmibus, wishbone2asmi, csr, wishbone2csr, dfi
6 6
 
7  
-from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy
  7
+from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii
8 8
 import constraints
9 9
 
10 10
 MHz = 1000000
@@ -12,6 +12,10 @@
12 12
 sram_size = 4096 # in bytes
13 13
 l2_size = 8192 # in bytes
14 14
 
  15
+dfi_a = 13
  16
+dfi_ba = 2
  17
+dfi_d = 128 # TODO -> 64
  18
+
15 19
 def ddrphy_clocking(crg, phy):
16 20
 	names = [
17 21
 		"clk2x_90",
@@ -31,12 +35,18 @@ def get():
31 35
 	#
32 36
 	# ASMI
33 37
 	#
34  
-	ddrphy0 = s6ddrphy.S6DDRPHY(1, 13, 2, 128)
35 38
 	asmihub0 = asmibus.Hub(23, 128, 12) # TODO: get hub from memory controller
36 39
 	asmiport_wb = asmihub0.get_port()
37 40
 	asmihub0.finalize()
38 41
 	
39 42
 	#
  43
+	# DFI
  44
+	#
  45
+	ddrphy0 = s6ddrphy.S6DDRPHY(1, dfi_a, dfi_ba, dfi_d)
  46
+	dfii0 = dfii.DFIInjector(2, dfi_a, dfi_ba, dfi_d, 2)
  47
+	dficon0 = dfi.Interconnect(dfii0.master, ddrphy0.dfi)
  48
+
  49
+	#
40 50
 	# WISHBONE
41 51
 	#
42 52
 	cpu0 = lm32.LM32()
@@ -70,7 +80,8 @@ def get():
70 80
 	uart0 = uart.UART(0, clk_freq, baud=115200)
71 81
 	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
72 82
 		uart0.bank.interface,
73  
-		ddrphy0.bank.interface
  83
+		ddrphy0.bank.interface,
  84
+		dfii0.bank.interface
74 85
 	])
75 86
 	
76 87
 	#

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