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Use migen.fhdl.std

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commit 611c4192b1f1a919511e612c717eaaaa99bcd180 1 parent 3eb41f7
Sébastien Bourdeauducq authored May 22, 2013

Showing 38 changed files with 55 additions and 91 deletions. Show diff stats Hide diff stats

  1. 3  milkymist/asmicon/__init__.py
  2. 3  milkymist/asmicon/bankmachine.py
  3. 9  milkymist/asmicon/multiplexer.py
  4. 3  milkymist/asmicon/refresher.py
  5. 3  milkymist/asmiprobe/__init__.py
  6. 5  milkymist/counteradc/__init__.py
  7. 11  milkymist/dfii/__init__.py
  8. 3  milkymist/dvisampler/__init__.py
  9. 3  milkymist/dvisampler/analysis.py
  10. 4  milkymist/dvisampler/chansync.py
  11. 3  milkymist/dvisampler/charsync.py
  12. 4  milkymist/dvisampler/clocking.py
  13. 4  milkymist/dvisampler/datacapture.py
  14. 3  milkymist/dvisampler/debug.py
  15. 3  milkymist/dvisampler/decoding.py
  16. 3  milkymist/dvisampler/dma.py
  17. 5  milkymist/dvisampler/edid.py
  18. 3  milkymist/dvisampler/wer.py
  19. 3  milkymist/framebuffer/__init__.py
  20. 3  milkymist/framebuffer/lib.py
  21. 7  milkymist/gpio/__init__.py
  22. 3  milkymist/identifier/__init__.py
  23. 4  milkymist/lm32/__init__.py
  24. 4  milkymist/m1crg/__init__.py
  25. 4  milkymist/minimac3/__init__.py
  26. 5  milkymist/norflash/__init__.py
  27. 12  milkymist/s6ddrphy/__init__.py
  28. 3  milkymist/timer/__init__.py
  29. 3  milkymist/uart/__init__.py
  30. 2  tb/asmicon/asmicon.py
  31. 2  tb/asmicon/asmicon_wb.py
  32. 2  tb/asmicon/bankmachine.py
  33. 2  tb/asmicon/common.py
  34. 2  tb/asmicon/refresher.py
  35. 2  tb/asmicon/selector.py
  36. 3  tb/dvisampler/chansync.py
  37. 2  tb/framebuffer/framebuffer.py
  38. 3  top.py
3  milkymist/asmicon/__init__.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.bus import dfi, asmibus
4 3
 
5 4
 from milkymist.asmicon.refresher import *
3  milkymist/asmicon/bankmachine.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.bus.asmibus import *
4 3
 from migen.genlib.roundrobin import *
5 4
 from migen.genlib.fsm import FSM
9  milkymist/asmicon/multiplexer.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.genlib.roundrobin import *
4 3
 from migen.genlib.misc import optree
5 4
 from migen.genlib.fsm import FSM
@@ -26,7 +25,7 @@ def __init__(self, requests, tagbits):
26 25
 		self.want_reads = Signal()
27 26
 		self.want_writes = Signal()
28 27
 		# NB: cas_n/ras_n/we_n are 1 when stb is inactive
29  
-		self.cmd = CommandRequestRW(len(requests[0].a), len(requests[0].ba), tagbits)
  28
+		self.cmd = CommandRequestRW(flen(requests[0].a), flen(requests[0].ba), tagbits)
30 29
 	
31 30
 		###
32 31
 
@@ -83,7 +82,7 @@ def stb_and(cmd, attr):
83 82
 
84 83
 class _Datapath(Module):
85 84
 	def __init__(self, timing_settings, command, dfi, hub):
86  
-		tagbits = len(hub.tag_call)
  85
+		tagbits = flen(hub.tag_call)
87 86
 		
88 87
 		rd_valid = Signal()
89 88
 		rd_tag = Signal(tagbits)
@@ -136,7 +135,7 @@ def __init__(self, phy_settings, geom_settings, timing_settings, bank_machines,
136 135
 	
137 136
 		# Command choosing
138 137
 		requests = [bm.cmd for bm in bank_machines]
139  
-		tagbits = len(hub.tag_call)
  138
+		tagbits = flen(hub.tag_call)
140 139
 		choose_cmd = _CommandChooser(requests, tagbits)
141 140
 		choose_req = _CommandChooser(requests, tagbits)
142 141
 		self.comb += [
3  milkymist/asmicon/refresher.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.genlib.misc import timeline
4 3
 from migen.genlib.fsm import FSM
5 4
 
3  milkymist/asmiprobe/__init__.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.bank.description import *
4 3
 
5 4
 class ASMIprobe(Module):
5  milkymist/counteradc/__init__.py
... ...
@@ -1,5 +1,6 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+import collections
  2
+
  3
+from migen.fhdl.std import *
3 4
 from migen.bank.description import *
4 5
 from migen.genlib.misc import optree
5 6
 from migen.genlib.cdc import MultiReg
11  milkymist/dfii/__init__.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.bus import dfi
4 3
 from migen.bank.description import *
5 4
 
@@ -7,10 +6,10 @@ class PhaseInjector(Module, AutoCSR):
7 6
 	def __init__(self, phase):
8 7
 		self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden
9 8
 		self._command_issue = CSR()
10  
-		self._address = CSRStorage(len(phase.address))
11  
-		self._baddress = CSRStorage(len(phase.bank))
12  
-		self._wrdata = CSRStorage(len(phase.wrdata))
13  
-		self._rddata = CSRStatus(len(phase.rddata))
  9
+		self._address = CSRStorage(flen(phase.address))
  10
+		self._baddress = CSRStorage(flen(phase.bank))
  11
+		self._wrdata = CSRStorage(flen(phase.wrdata))
  12
+		self._rddata = CSRStatus(flen(phase.rddata))
14 13
 	
15 14
 		###
16 15
 
3  milkymist/dvisampler/__init__.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.bank.description import AutoCSR
4 3
 
5 4
 from milkymist.dvisampler.edid import EDID
3  milkymist/dvisampler/analysis.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.genlib.cdc import MultiReg
4 3
 from migen.genlib.fifo import AsyncFIFO
5 4
 from migen.genlib.record import Record
4  milkymist/dvisampler/chansync.py
... ...
@@ -1,6 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.specials import Memory
3  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
4 2
 from migen.genlib.cdc import MultiReg
5 3
 from migen.genlib.fifo import _inc
6 4
 from migen.genlib.record import Record, layout_len
3  milkymist/dvisampler/charsync.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.genlib.cdc import MultiReg
4 3
 from migen.genlib.misc import optree
5 4
 from migen.bank.description import *
4  milkymist/dvisampler/clocking.py
... ...
@@ -1,6 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
3  
-from migen.fhdl.specials import Instance
  1
+from migen.fhdl.std import *
4 2
 from migen.genlib.cdc import MultiReg
5 3
 from migen.bank.description import *
6 4
 
4  milkymist/dvisampler/datacapture.py
... ...
@@ -1,6 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
3  
-from migen.fhdl.specials import Instance
  1
+from migen.fhdl.std import *
4 2
 from migen.genlib.cdc import MultiReg, PulseSynchronizer
5 3
 from migen.bank.description import *
6 4
 
3  milkymist/dvisampler/debug.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.genlib.fifo import AsyncFIFO
4 3
 from migen.genlib.record import layout_len
5 4
 from migen.bank.description import AutoCSR
3  milkymist/dvisampler/decoding.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.genlib.record import Record
4 3
 
5 4
 from milkymist.dvisampler.common import control_tokens, channel_layout
3  milkymist/dvisampler/dma.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.genlib.fsm import FSM
4 3
 from migen.bank.description import *
5 4
 from migen.bank.eventmanager import *
5  milkymist/dvisampler/edid.py
... ...
@@ -1,6 +1,5 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.specials import Memory, Tristate
3  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
  2
+from migen.fhdl.specials import Tristate
4 3
 from migen.genlib.cdc import MultiReg
5 4
 from migen.genlib.fsm import FSM
6 5
 from migen.genlib.misc import chooser
3  milkymist/dvisampler/wer.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.bank.description import *
4 3
 from migen.genlib.misc import optree
5 4
 from migen.genlib.cdc import PulseSynchronizer
3  milkymist/framebuffer/__init__.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.flow.actor import *
4 3
 from migen.flow.network import *
5 4
 from migen.bank.description import CSRStorage, AutoCSR
3  milkymist/framebuffer/lib.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.genlib.record import Record
4 3
 from migen.genlib.fifo import AsyncFIFO
5 4
 from migen.flow.actor import *
7  milkymist/gpio/__init__.py
... ...
@@ -1,16 +1,15 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.genlib.cdc import MultiReg
4 3
 from migen.bank.description import *
5 4
 
6 5
 class GPIOIn(Module, AutoCSR):
7 6
 	def __init__(self, signal):
8  
-		self._r_in = CSRStatus(len(signal))
  7
+		self._r_in = CSRStatus(flen(signal))
9 8
 		self.specials += MultiReg(signal, self._r_in.status)
10 9
 
11 10
 class GPIOOut(Module, AutoCSR):
12 11
 	def __init__(self, signal):
13  
-		self._r_out = CSRStorage(len(signal))
  12
+		self._r_out = CSRStorage(flen(signal))
14 13
 		self.comb += signal.eq(self._r_out.storage)
15 14
 
16 15
 class Blinker(Module):
3  milkymist/identifier/__init__.py
... ...
@@ -1,7 +1,6 @@
1 1
 import re
2 2
 
3  
-from migen.fhdl.structure import *
4  
-from migen.fhdl.module import Module
  3
+from migen.fhdl.std import *
5 4
 from migen.bank.description import *
6 5
 
7 6
 def encode_version(version):
4  milkymist/lm32/__init__.py
... ...
@@ -1,6 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.specials import Instance
3  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
4 2
 from migen.bus import wishbone
5 3
 
6 4
 class LM32(Module):
4  milkymist/m1crg/__init__.py
... ...
@@ -1,8 +1,6 @@
1 1
 from fractions import Fraction
2 2
 
3  
-from migen.fhdl.structure import *
4  
-from migen.fhdl.specials import Instance
5  
-from migen.fhdl.module import Module
  3
+from migen.fhdl.std import *
6 4
 from migen.bank.description import *
7 5
 
8 6
 class M1CRG(Module, AutoCSR):
4  milkymist/minimac3/__init__.py
... ...
@@ -1,6 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.specials import Instance
3  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
4 2
 from migen.bank.description import *
5 3
 from migen.bank.eventmanager import *
6 4
 from migen.bus import wishbone
5  milkymist/norflash/__init__.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.bus import wishbone
4 3
 from migen.genlib.misc import timeline
5 4
 
@@ -9,7 +8,7 @@ def __init__(self, pads, rd_timing):
9 8
 	
10 9
 		###
11 10
 
12  
-		adr_width = len(pads.adr) + 1
  11
+		adr_width = flen(pads.adr) + 1
13 12
 		self.comb += [pads.oe_n.eq(0), pads.we_n.eq(1),
14 13
 			pads.ce_n.eq(0)]
15 14
 		self.sync += timeline(self.bus.cyc & self.bus.stb, [
12  milkymist/s6ddrphy/__init__.py
... ...
@@ -1,20 +1,18 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.specials import Instance
3  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
4 2
 from migen.bus import dfi
5 3
 
6 4
 class S6DDRPHY(Module):
7 5
 	def __init__(self, pads):
8  
-		self.dfi = dfi.Interface(len(pads.a), len(pads.ba), 2*len(pads.dq), 2)
  6
+		self.dfi = dfi.Interface(flen(pads.a), flen(pads.ba), 2*flen(pads.dq), 2)
9 7
 		self.clk4x_wr_strb = Signal()
10 8
 		self.clk4x_rd_strb = Signal()
11 9
 
12 10
 		###
13 11
 
14 12
 		inst_items = [
15  
-			Instance.Parameter("NUM_AD", len(pads.a)),
16  
-			Instance.Parameter("NUM_BA", len(pads.ba)),
17  
-			Instance.Parameter("NUM_D", 2*len(pads.dq)),
  13
+			Instance.Parameter("NUM_AD", flen(pads.a)),
  14
+			Instance.Parameter("NUM_BA", flen(pads.ba)),
  15
+			Instance.Parameter("NUM_D", 2*flen(pads.dq)),
18 16
 
19 17
 			Instance.Input("sys_clk", ClockSignal()),
20 18
 			Instance.Input("clk2x_270", ClockSignal("sys2x_270")),
3  milkymist/timer/__init__.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.bank.description import *
4 3
 from migen.bank.eventmanager import *
5 4
 
3  milkymist/uart/__init__.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.genlib.cdc import MultiReg
4 3
 from migen.bank.description import *
5 4
 from migen.bank.eventmanager import *
2  tb/asmicon/asmicon.py
... ...
@@ -1,4 +1,4 @@
1  
-from migen.fhdl.structure import *
  1
+from migen.fhdl.std import *
2 2
 from migen.bus.asmibus import *
3 3
 from migen.sim.generic import Simulator, TopLevel
4 4
 
2  tb/asmicon/asmicon_wb.py
... ...
@@ -1,4 +1,4 @@
1  
-from migen.fhdl.structure import *
  1
+from migen.fhdl.std import *
2 2
 from migen.bus import wishbone, wishbone2asmi, asmibus
3 3
 from migen.sim.generic import Simulator, TopLevel
4 4
 
2  tb/asmicon/bankmachine.py
... ...
@@ -1,4 +1,4 @@
1  
-from migen.fhdl.structure import *
  1
+from migen.fhdl.std import *
2 2
 from migen.bus.asmibus import *
3 3
 from migen.sim.generic import Simulator, TopLevel
4 4
 
2  tb/asmicon/common.py
... ...
@@ -1,7 +1,7 @@
1 1
 from fractions import Fraction
2 2
 from math import ceil
3 3
 
4  
-from migen.fhdl.structure import *
  4
+from migen.fhdl.std import *
5 5
 from migen.sim.generic import Proxy
6 6
 
7 7
 from milkymist import asmicon
2  tb/asmicon/refresher.py
... ...
@@ -1,6 +1,6 @@
1 1
 from random import Random
2 2
 
3  
-from migen.fhdl.structure import *
  3
+from migen.fhdl.std import *
4 4
 from migen.sim.generic import Simulator, TopLevel
5 5
 
6 6
 from milkymist.asmicon.refresher import *
2  tb/asmicon/selector.py
... ...
@@ -1,6 +1,6 @@
1 1
 from random import Random
2 2
 
3  
-from migen.fhdl.structure import *
  3
+from migen.fhdl.std import *
4 4
 from migen.bus.asmibus import *
5 5
 from migen.sim.generic import Simulator, TopLevel
6 6
 
3  tb/dvisampler/chansync.py
... ...
@@ -1,5 +1,4 @@
1  
-from migen.fhdl.structure import *
2  
-from migen.fhdl.module import Module
  1
+from migen.fhdl.std import *
3 2
 from migen.sim.generic import *
4 3
 
5 4
 from milkymist.dvisampler.chansync import ChanSync
2  tb/framebuffer/framebuffer.py
... ...
@@ -1,4 +1,4 @@
1  
-from migen.fhdl.structure import *
  1
+from migen.fhdl.std import *
2 2
 from migen.bus import asmibus
3 3
 from migen.sim.generic import Simulator
4 4
 
3  top.py
@@ -2,8 +2,7 @@
2 2
 from math import ceil
3 3
 from operator import itemgetter
4 4
 
5  
-from migen.fhdl.structure import *
6  
-from migen.fhdl.module import Module
  5
+from migen.fhdl.std import *
7 6
 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
8 7
 from migen.bank import csrgen
9 8
 

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