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Use meaningful class names

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commit 6fde54c5aa89838c9277bfa948a6083392a63285 1 parent f6aa95a
Sébastien Bourdeauducq authored January 21, 2012
2  milkymist/clkfx/__init__.py
@@ -2,7 +2,7 @@
2 2
 
3 3
 from migen.fhdl.structure import *
4 4
 
5  
-class Inst:
  5
+class ClkFX:
6 6
 	def __init__(self, infreq, outfreq):
7 7
 		self.clkin = Signal()
8 8
 		self.clkout = Signal()
2  milkymist/lm32/__init__.py
... ...
@@ -1,7 +1,7 @@
1 1
 from migen.fhdl.structure import *
2 2
 from migen.bus import wishbone
3 3
 
4  
-class Inst:
  4
+class LM32:
5 5
 	def __init__(self):
6 6
 		self.ibus = i = wishbone.Master("lm32i")
7 7
 		self.dbus = d = wishbone.Master("lm32d")
2  milkymist/m1reset/__init__.py
... ...
@@ -1,6 +1,6 @@
1 1
 from migen.fhdl.structure import *
2 2
 
3  
-class Inst:
  3
+class M1Reset:
4 4
 	def __init__(self):
5 5
 		self.trigger_reset = Signal()
6 6
 		self.sys_rst = Signal()
4  milkymist/norflash/__init__.py
@@ -2,7 +2,7 @@
2 2
 from migen.bus import wishbone
3 3
 from migen.corelogic import timeline
4 4
 
5  
-class Inst:
  5
+class NorFlash:
6 6
 	def __init__(self, adr_width, rd_timing):
7 7
 		self.bus = wishbone.Slave("norflash")
8 8
 		self.adr = Signal(BV(adr_width-1))
@@ -10,7 +10,7 @@ def __init__(self, adr_width, rd_timing):
10 10
 		self.oe_n = Signal()
11 11
 		self.we_n = Signal()
12 12
 		self.ce_n = Signal()
13  
-		self.timeline = timeline.Inst(self.bus.cyc_i & self.bus.stb_i,
  13
+		self.timeline = timeline.Timeline(self.bus.cyc_i & self.bus.stb_i,
14 14
 			[(0, [self.adr.eq(Cat(0, self.bus.adr_i[:adr_width-2]))]),
15 15
 			(rd_timing, [
16 16
 				self.bus.dat_o[16:].eq(self.d),
2  milkymist/uart/__init__.py
@@ -2,7 +2,7 @@
2 2
 from migen.bank.description import *
3 3
 from migen.bank import csrgen
4 4
 
5  
-class Inst:
  5
+class UART:
6 6
 	def __init__(self, address, clk_freq, baud=115200):
7 7
 		self._rxtx = rxtx = Register("rxtx", BV(8))
8 8
 		divisor = Register("divisor")
12  top.py
@@ -9,18 +9,18 @@ def get():
9 9
 	MHz = 1000000
10 10
 	clk_freq = 80*MHz
11 11
 	
12  
-	clkfx_sys = clkfx.Inst(50*MHz, clk_freq)
13  
-	reset0 = m1reset.Inst()
  12
+	clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
  13
+	reset0 = m1reset.M1Reset()
14 14
 	
15  
-	cpu0 = lm32.Inst()
16  
-	norflash0 = norflash.Inst(25, 12)
17  
-	wishbone2csr0 = wishbone2csr.Inst()
  15
+	cpu0 = lm32.LM32()
  16
+	norflash0 = norflash.NorFlash(25, 12)
  17
+	wishbone2csr0 = wishbone2csr.WB2CSR()
18 18
 	wishbonecon0 = wishbone.InterconnectShared(
19 19
 		[cpu0.ibus, cpu0.dbus],
20 20
 		[(0, norflash0.bus), (3, wishbone2csr0.wishbone)],
21 21
 		register=True,
22 22
 		offset=1)
23  
-	uart0 = uart.Inst(0, clk_freq, baud=115200)
  23
+	uart0 = uart.UART(0, clk_freq, baud=115200)
24 24
 	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
25 25
 	
26 26
 	frag = autofragment.from_local()

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