From 6fde54c5aa89838c9277bfa948a6083392a63285 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 21 Jan 2012 12:25:22 +0100 Subject: [PATCH] Use meaningful class names --- milkymist/clkfx/__init__.py | 2 +- milkymist/lm32/__init__.py | 2 +- milkymist/m1reset/__init__.py | 2 +- milkymist/norflash/__init__.py | 4 ++-- milkymist/uart/__init__.py | 2 +- top.py | 12 ++++++------ 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/milkymist/clkfx/__init__.py b/milkymist/clkfx/__init__.py index 2e65f089a..e90183ebe 100644 --- a/milkymist/clkfx/__init__.py +++ b/milkymist/clkfx/__init__.py @@ -2,7 +2,7 @@ from migen.fhdl.structure import * -class Inst: +class ClkFX: def __init__(self, infreq, outfreq): self.clkin = Signal() self.clkout = Signal() diff --git a/milkymist/lm32/__init__.py b/milkymist/lm32/__init__.py index 26b47947e..324595419 100644 --- a/milkymist/lm32/__init__.py +++ b/milkymist/lm32/__init__.py @@ -1,7 +1,7 @@ from migen.fhdl.structure import * from migen.bus import wishbone -class Inst: +class LM32: def __init__(self): self.ibus = i = wishbone.Master("lm32i") self.dbus = d = wishbone.Master("lm32d") diff --git a/milkymist/m1reset/__init__.py b/milkymist/m1reset/__init__.py index 71612538e..64b973b99 100644 --- a/milkymist/m1reset/__init__.py +++ b/milkymist/m1reset/__init__.py @@ -1,6 +1,6 @@ from migen.fhdl.structure import * -class Inst: +class M1Reset: def __init__(self): self.trigger_reset = Signal() self.sys_rst = Signal() diff --git a/milkymist/norflash/__init__.py b/milkymist/norflash/__init__.py index ccb2c1f10..0ee19ec27 100644 --- a/milkymist/norflash/__init__.py +++ b/milkymist/norflash/__init__.py @@ -2,7 +2,7 @@ from migen.bus import wishbone from migen.corelogic import timeline -class Inst: +class NorFlash: def __init__(self, adr_width, rd_timing): self.bus = wishbone.Slave("norflash") self.adr = Signal(BV(adr_width-1)) @@ -10,7 +10,7 @@ def __init__(self, adr_width, rd_timing): self.oe_n = Signal() self.we_n = Signal() self.ce_n = Signal() - self.timeline = timeline.Inst(self.bus.cyc_i & self.bus.stb_i, + self.timeline = timeline.Timeline(self.bus.cyc_i & self.bus.stb_i, [(0, [self.adr.eq(Cat(0, self.bus.adr_i[:adr_width-2]))]), (rd_timing, [ self.bus.dat_o[16:].eq(self.d), diff --git a/milkymist/uart/__init__.py b/milkymist/uart/__init__.py index 2e83cbe14..42f763ca2 100644 --- a/milkymist/uart/__init__.py +++ b/milkymist/uart/__init__.py @@ -2,7 +2,7 @@ from migen.bank.description import * from migen.bank import csrgen -class Inst: +class UART: def __init__(self, address, clk_freq, baud=115200): self._rxtx = rxtx = Register("rxtx", BV(8)) divisor = Register("divisor") diff --git a/top.py b/top.py index d865a3c50..a2097b81f 100644 --- a/top.py +++ b/top.py @@ -9,18 +9,18 @@ def get(): MHz = 1000000 clk_freq = 80*MHz - clkfx_sys = clkfx.Inst(50*MHz, clk_freq) - reset0 = m1reset.Inst() + clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq) + reset0 = m1reset.M1Reset() - cpu0 = lm32.Inst() - norflash0 = norflash.Inst(25, 12) - wishbone2csr0 = wishbone2csr.Inst() + cpu0 = lm32.LM32() + norflash0 = norflash.NorFlash(25, 12) + wishbone2csr0 = wishbone2csr.WB2CSR() wishbonecon0 = wishbone.InterconnectShared( [cpu0.ibus, cpu0.dbus], [(0, norflash0.bus), (3, wishbone2csr0.wishbone)], register=True, offset=1) - uart0 = uart.Inst(0, clk_freq, baud=115200) + uart0 = uart.UART(0, clk_freq, baud=115200) csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface]) frag = autofragment.from_local()