Skip to content
This repository

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
Browse code

framebuffer/dvi: add TMDS encoder (untested)

  • Loading branch information...
commit 78587d1eaabd60008abfb570567631eb58c79862 1 parent d421aae
Sébastien Bourdeauducq authored September 16, 2013

Showing 1 changed file with 88 additions and 0 deletions. Show diff stats Hide diff stats

  1. 88  milkymist/framebuffer/dvi.py
88  milkymist/framebuffer/dvi.py
... ...
@@ -0,0 +1,88 @@
  1
+from migen.fhdl.std import *
  2
+from migen.genlib.misc import optree
  3
+
  4
+control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]
  5
+
  6
+class Encoder(Module):
  7
+	def __init__(self):
  8
+		self.d = Signal(8)
  9
+		self.c = Signal(2)
  10
+		self.de = Signal()
  11
+
  12
+		self.output = Signal(10)
  13
+
  14
+		###
  15
+
  16
+		# stage 1 - count number of 1s in data
  17
+		d = Signal(8)
  18
+		n1d = Signal(max=9)
  19
+		self.sync += [
  20
+			n1d.eq(optree("+", [self.d[i] for i in range(8)])),
  21
+			d.eq(self.d)
  22
+		]
  23
+
  24
+		# stage 2 - add 9th bit
  25
+		q_m = Signal(9)
  26
+		q_m8_n = Signal()
  27
+		self.comb += q_m8_n.eq((n1d > 4) | ((n1d == 4) & ~d[0]))
  28
+		for i in range(8):
  29
+			if i:
  30
+				curval = curval ^ d[i] ^ q_m8_n	
  31
+			else:
  32
+				curval = d[0]		
  33
+			self.sync += q_m[i].eq(curval)
  34
+		self.sync += q_m[8].eq(~q_m8_n)
  35
+
  36
+		# stage 3 - count number of 1s and 0s in q_m[:8]
  37
+		q_m_r = Signal(9)
  38
+		n0q_m = Signal(max=9)
  39
+		n1q_m = Signal(max=9)
  40
+		self.sync += [
  41
+			n0q_m.eq(optree("+", [~q_m[i] for i in range(8)])),
  42
+			n1q_m.eq(optree("+", [q_m[i] for i in range(8)])),
  43
+			q_m_r.eq(q_m)
  44
+		]
  45
+
  46
+		# stage 4 - final encoding
  47
+		cnt = Signal((5, True))
  48
+
  49
+		s_c = self.c
  50
+		s_de = self.de
  51
+		for p in range(3):
  52
+			new_c = Signal(2)
  53
+			new_de = Signal()
  54
+			self.sync += new_c.eq(s_c), new_de.eq(s_de)
  55
+			s_c, s_de = new_c, new_de
  56
+
  57
+		self.sync += If(s_de,
  58
+				If((cnt == 0) | (n1q_m == n0q_m),
  59
+					self.output[9].eq(~q_m_r[8]),
  60
+					self.output[8].eq(q_m_r[8]),
  61
+					If(q_m_r[8],
  62
+						self.output[:8].eq(q_m_r[:8]),
  63
+						cnt.eq(cnt + n1q_m - n0q_m)
  64
+					).Else(
  65
+						self.output[:8].eq(~q_m_r[:8]),
  66
+						cnt.eq(cnt + n0q_m - n1q_m)
  67
+					)
  68
+				).Else(
  69
+					If((~cnt[4] & (n1q_m > n0q_m)) | (cnt[4] & (n0q_m > n1q_m)),
  70
+						self.output[9].eq(1),
  71
+						self.output[8].eq(q_m_r[8]),
  72
+						self.output[:8].eq(~q_m_r[:8]),
  73
+						cnt.eq(cnt + Cat(0, q_m_r[8]) + n0q_m - n1q_m)
  74
+					).Else(
  75
+						self.output[9].eq(0),
  76
+						self.output[8].eq(q_m_r[8]),
  77
+						self.output[:8].eq(q_m_r[:8]),
  78
+						cnt.eq(cnt - Cat(0, ~q_m_r[8]) + n1q_m - n0q_m)
  79
+					)
  80
+				)
  81
+			).Else(
  82
+				self.output.eq(Array(control_tokens)[s_c]),
  83
+				cnt.eq(0)
  84
+			)
  85
+
  86
+if __name__ == "__main__":
  87
+	from migen.fhdl import verilog
  88
+	print(verilog.convert(Encoder()))

0 notes on commit 78587d1

Please sign in to comment.
Something went wrong with that request. Please try again.