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m1crg: fix signal names

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commit 7ad2f7081bf1c6d7d33f11b1045fbd6e350503d3 1 parent 5649e88
Sébastien Bourdeauducq authored February 13, 2013
2  load.jtag
@@ -2,4 +2,4 @@ cable milkymist
2 2
 detect
3 3
 instruction CFG_OUT  000100 BYPASS
4 4
 instruction CFG_IN   000101 BYPASS
5  
-pld load build/soc.bit
  5
+pld load build/top.bit
6  verilog/m1crg/m1crg.v
@@ -204,7 +204,7 @@ ODDR2 #(
204 204
 	.INIT(1'b0),
205 205
 	.SRTYPE("SYNC")
206 206
 ) sd_clk_forward_p (
207  
-	.Q(sd_clk_out_p),
  207
+	.Q(ddr_clk_pad_p),
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 	.C0(clk2x_270),
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 	.C1(~clk2x_270),
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 	.CE(1'b1),
@@ -218,7 +218,7 @@ ODDR2 #(
218 218
 	.INIT(1'b0),
219 219
 	.SRTYPE("SYNC")
220 220
 ) sd_clk_forward_n (
221  
-	.Q(sd_clk_out_n),
  221
+	.Q(ddr_clk_pad_n),
222 222
 	.C0(clk2x_270),
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 	.C1(~clk2x_270),
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 	.CE(1'b1),
@@ -233,7 +233,7 @@ ODDR2 #(
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  */
234 234
 
235 235
 always @(posedge pllout4)
236  
-	eth_clk_pad <= ~eth_clk_pad;
  236
+	eth_phy_clk_pad <= ~eth_phy_clk_pad;
237 237
 
238 238
 /* Let the synthesizer insert the appropriate buffers */
239 239
 assign eth_rx_clk = eth_rx_clk_pad;

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